Patent Grant
9996461
This disclosure relates to storage devices in which a mapping of addresses in stored. More particularly, this disclosure relates to dynamic differential compression of information related to such a mapping.
The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
Data storage devices such as disk drives, including solid-state drives, store data at physical locations, while a host system with which the storage device is associated may refer to the same data with reference to logical locations. In order to be able to store and retrieve the data, the storage device controller maintains a mapping between the physical locations and the logical locations. The mapping data may occupy substantial space. For example, in some systems the mapping data may occupy one megabyte for every gigabyte of user data.
A method according to implementations of this disclosure for storing data on a storage device includes receiving data to be stored and a received logical address for storing the data to be stored, determining a physical address and storing the data to be stored at the determined physical address, examining a table that associates logical addresses with physical addresses to determine a difference relationship between the determined physical address and a corresponding physical address for one of other logical addresses, and storing in the table, in association with the received logical address, information representing the determined physical address as a function of the determined difference relationship.
A data storage device according to implementations of this disclosure includes controller circuitry and memory for storing a lookup table that associates logical addresses with physical addresses. The controller circuitry receives data to be stored and a received logical address for storing the data to be stored, determines a physical address on a storage medium and sends the data to be stored to the determined physical address on the storage medium for storage, examines the lookup table to determine a difference relationship between the determined physical address and a corresponding physical address for one of other logical addresses, and stores in the lookup table, in association with the received logical address, the determined physical address as a function of the determined difference relationship.
Further features of the disclosure, its nature and various advantages, will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
Data may be stored in storage devices in units referred to as allocation units (AUs). Each allocation unit may have a physical location, or physical allocation unit address (PAA), at which it is stored, as well as a logical location, or logical allocation unit address (LAA), at which, for example, a host system considers the data in the allocation unit to located. A user logical block address (LBA) may be mapped into an LAA based on the sector number in an AU. In order to be able to store and retrieve the data, the storage device controller maintains a mapping between the logical locations and the physical locations. The mapping data may occupy substantial space. For example, in some systems the mapping data may occupy one megabyte for every gigabyte of user data.
Storage controller 103 includes a microcontroller 113, working memory 123, and nonvolatile memory 133. The aforementioned mapping data may be stored in nonvolatile memory 133 which could be, e.g., NAND Flash memory. When storage device 101 is powered on, the mapping data may be copied from nonvolatile memory 133 to working memory 123 which could be, e.g., double-data-rate (DDR) dynamic random access memory (DRAM).
A portion of an example of the mapping data may be a look-up table (LUT), as follows:
Each LUT entry is 32 bits or 4 bytes, represented by an eight-character hexadecimal number. Each LUT entry corresponds to an LAA, which represents one AU. The content of a LUT entry is the corresponding PAA of that AU. The PAA encodes a physical address in or on storage medium 102, including channel, device, logical unit number (LUN), sector, block, row address, AU index within a page, etc. Each entry in the far left column is the address in the DRAM where the first of the LUT entries in that row is located, with the remaining LUT entries following in succession.
As noted above, the mapping data in its native form may occupy one megabyte for every gigabyte of user data. Because DDR DRAM is relatively expensive, the mapping data may be compressed in accordance with implementations of this disclosure.
One form of compression is differential compression. If adjacent data values are sufficiently close that the differential or difference relationship between them can be expressed in fewer bits or bytes than expressing the values themselves, then after the first value, each subsequent value can be stored in terms of its differential from the previous value.
Known forms of differential compression provide a fixed number of bytes for expressing the differential between entries. However, in a completely generic case, the differential values of adjacent eight-character entries in the LUT can vary in a large range. If a small number of bytes is reserved for the differential value, that would limit the coverage of the differential compression scheme—i.e., the situations in which differential compression can be used to compress the PAA LUT. Conversely, if a large number of bytes is reserved for the differential value, then the compression is not efficient for data sequences with small differential values.
In accordance with implementations of this disclosure, a dynamic differential compression scheme, in which the number of bytes used to express the differential can change, balances the coverage and efficiency of using differential coding to compress the PAA LUT. According to the dynamic differential compression scheme, a packet header is added at the beginning of the compressed data packet to indicate a packet type and the number of eight-character values in the packet.
In one implementation, seven types of packets (numbered 0-6) may be identified:
Therefore, the three most significant bits [7:5] of the packet header are used to represent the packet type. The five least significant bits [4:0] of the packet header are used to indicate the number of PAAs in the packet as a zero-based number where 0 signifies one packet, meaning that a packet can contain up to 32 PAAs. The structure of such a packet header 200 is shown in
In accordance with implementations of this disclosure, the data in the LUT that maps the LAAs to the PAAs normally will include a mix of packet types. While Type 6 packets are actually larger than the data they replace, the mix of packet types normally would be such that the overall LUT size is reduced.
Unless the first LAA to be mapped represents an invalid address, at least a portion of the mapping data for the first LAA would be stored as a Type 6 packet without compression, and subsequent chunks of mapping data could be compressed in accordance with this disclosure, as discussed below. If the first LAA to be mapped represents an invalid address, then even the initial entry can be compressed into a Type 0 packet.
For example, in the sample LUT above, the first PAA is invalid, the second PAA is 00EB8C88, and the third PAA is 00EB8C79. The first PAA would be represented by a Type 0 packet containing one PAA. Because the difference between the second packet and the first packet is larger than can be represented by three bytes, and because the difference between the third packet and the second packet is negative (−9 hex), the second and third PAAs would be represented by a Type 6 packet in which each PAA is included without compression. The next three PAAs are consecutive with the third PAA, and therefore would be represented by a Type 1 packet indicating three PAAs, and so on.
Each raw chunk of mapping data of a given size would be divided into packets, with the packets compressed as discussed above and then recombined into a compressed chunk of mapping data.
As shown in histogram 1000 in
As shown in histogram 1200 in
As shown in histogram 1400
From these examples, it can be seen that compression ratios improve as chunk size increases. That is to be expected, because larger chunks require less overhead per unit of data. However, as chunk size increases, latency may increase, so in selecting the chunk size, there is a trade-off between latency and compression ratio.
Returning to the discussion of
When reading data, when microcontroller 113 reads the LAA-PAA LUT to determine the PAA 141 for the data 144 sought by the host, microcontroller 113 reconstructs the desired PAA from the table in working memory 123 by reading the closest previous complete PAA and the intervening difference data.
A method 160 that could be used by microcontroller 113 in accordance with this disclosure to write to the LAA-PAA LUT upon receiving data to store from the host is diagrammed in
At 161, data to be written and an LAA location are received from the host. At 162, an available location on storage medium 162 to which the data can be written, and the PAA of that location, are determined by microcontroller 165. At 163, the data are written to that location.
At 164, the relationship between the newly-determined PAA, which is to be associated with the LAA provided by the host, and the PAAs of surrounding LAAs in the LAA-PAA LUT is determined. That is, the differentials between the new PAA and the neighboring PAAs are determined.
At 165, the LUT is adjusted accordingly; that is, if the differentials are in same packet-type category as the previous PAA for that LAA, then the packet structure in the LUT is not changed, but the individual differentials changed. But if the differentials are such that the packet-type categories have to change, then in addition to updating the differentials, the packet structure of the LUT is re-arranged so that the current PAA and the adjacent PAAs are in packets of the correct type based on the new differentials. Where the new differentials mean that PAAs that were in one packet can no longer be in one packet because at least one is further apart from the others, packets will have to be broken up and new packets created. Where the new differentials mean that PAAs that were in different packets are now close enough to be in one packet, packets may be merged.
After any adjustments at 165, method 160 ends.
A method 170 that could be used by microcontroller 113 in accordance with this disclosure to read the LAA-PAA LUT upon receiving a request from the host to read data is diagrammed in
At 171, a data read request, including an LAA, is received from the host. At 172, the LAA entry in the LUT is examined to determine the PAA. At 173, it is determined whether the PAA in the LUT is a full PAA, or is indicated by a differential from another PAA. If at 173 it is determined that the PAA is a full PAA, then at 174, data is read from that PAA and method 170 ends.
If at 173 it is determined that the PAA is indicated by a differential from another PAA, then at 175 that other PAA is located. At 176, all differentials between that other PAA and the current PAA are read, and at 177 the differentials are used to reconstruct the current PAA from the other PAA. The requested data are then read at 174 and method 170 ends.
It will be understood that the foregoing is only illustrative of the principles of the invention, and that the invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims which follow.
This claims the benefit of commonly-assigned U.S. Provisional Patent Application No. 62/054,699, filed Sep. 24, 2014, which is hereby incorporated by reference herein in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 9569348 | Deming | Feb 2017 | B1 |
| 20110072235 | Deming | Mar 2011 | A1 |
| 20130246689 | Matsudaira | Sep 2013 | A1 |
| 20150143025 | Gorobets | May 2015 | A1 |
| 20150379737 | Nilsson | Dec 2015 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 62054699 | Sep 2014 | US |
