DYNAMIC INCREMENTAL COMPILER AND METHOD

Abstract

A virtual machine executive (VME) system operating on a target platform that includes a virtual machine monitor (VMM) and a dynamic compiler, in particular, a trace compiler (TC). System embodiments include a virtual machine monitor configured to record a trace corresponding to a selected cycle, and configured to transform the trace into a representation of a trace tree; and a trace compiler cooperating with the virtual machine monitor to compile the representation of the trace tree into a compiled code segment of native machine code executable on the target platform, in which the trace is a linear instruction sequence traversing at least a portion of a method, a loop, or a branching node.

Description

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is an illustration of a program code stub illustrating principles pertinent to the present disclosure;

FIG. 1B is an illustration of a program flow diagram, corresponding to the illustration of FIG. 1;

FIG. 2 is a graphical depiction of a target platform capable of operating selected disclosed embodiments;

FIG. 3 is a flow diagram generally illustrating a method for dynamic compilation, in accordance with the present disclosure;

FIG. 4 is a flow diagram generally depicting a present trace selection method;

FIG. 5 is flow diagram generally depicting a method for recording a trace, in accordance with the present disclosure;

FIG. 6 is a flow diagram generally illustrating a method for generating a trace tree, in accordance with the present disclosure;

FIG. 7 illustrates trace data structures and trace SSA data structures, generally corresponding to FIGS. 1A and 1B; and

FIG. 8 illustrates a method for compiling native code in a reverse order, in accordance with the present disclosure.

Claims

1. A system executed on a target platform, comprising: a virtual machine monitor configured to record a trace corresponding to a selected cycle, and configured to transform the trace into a representation of a trace tree; anda trace compiler cooperating with the virtual machine monitor to compile the representation of the trace tree into a compiled code segment of native machine code executable on the target platform,wherein the trace is a linear instruction sequence traversing at least a portion of a method, a loop, or a branching node.

2. The system of claim 1, wherein the representation of the trace tree is implicit.

3. The system of claim 1, wherein the trace comprises a primary trace and at least one secondary trace ordered in a predetermined forward succession sequence.

4. The system of claim 1, wherein the trace compiler transforms the trace from a first computer code corresponding to a first computer architecture to a second computer code corresponding to a second computer architecture.

5. The system of claim 1, wherein the loop comprises multiple internal paths.

6. The system of claim 1, further comprising a virtual code interpreter cooperating with the virtual machine monitor to record as the trace virtual machine code instructions corresponding to a selected cycle.

7. The system of claim 2, wherein the trace comprises a primary trace and at least one secondary trace ordered in a predetermined forward succession sequence.

8. The system of claim 6, wherein the virtual machine monitor causes the compiled code segment corresponding to an application program to be executed, wherein the compiled code segment includes a bailout condition terminating program execution, and wherein the virtual code interpreter cooperates with the virtual machine monitor to resume program execution at an application program location corresponding to the bailout condition.

9. The system of claim 7, wherein the trace compiler is configured to compile the representation of the trace tree in reverse of the predetermined forward succession sequence.

10. The system of claim 9, wherein the method comprises a dynamically dispatched method, wherein the loop comprises multiple internal paths, or both.

11. The system of claim 1, wherein the target platform is a constrained-resource platform, including one of a mobile wireless device, a handheld device, a personal digital assistant, or a personal communication device.

12. A virtual processor for a target platform, comprising: a trace compiler, configured to monitor execution of a virtual code instruction sequence on a virtual code interpreter, configured to record a portion of the instruction sequence including at least a portion of a method, and configured to dynamically compile the trace as an executable compiled code segment, wherein the target platform is a constrained-resource target platform.

13. The virtual processor of claim 12, wherein the trace compiler comprises a dynamic, incremental trace compiler.

14. The virtual processor of claim 12, wherein the method comprises a dynamically dispatched method.

15. A method for operating a constrained-resource target platform, comprising: monitoring execution of selected instructions to identify a cycle therein;monitoring an execution frequency of the cycle;selecting the cycle as a primary trace in response to the execution frequency being equal to or greater than a predetermined cycle threshold frequency;recording execution of cycle instructions as recorded trace code;optimizing the recorded trace code in a trace tree static single assignment form (TTSSA) generating a representation of a TTSSA trace tree; andcompiling the representation of the TTSSA trace tree into native machine code in reverse of a predetermined succession sequence.

16. The method of claim 15, wherein the cycle instructions traverse at least a portion of a method.

17. The method of claim 15, further comprising successively selecting alternative cycle paths as a succession of secondary traces arranged in the predetermined succession sequence.

18. The method of claim 17, wherein the cycle instructions traverse at least a portion of a dynamically dispatched method.

19. The method of claim 18, wherein an activation record is not generated for the dynamically dispatched method.

20. A method for dynamic compilation, comprising: transforming an executed virtual code representation into a trace code representation in trace tree static single assignment (TTSSA) form wherein trace code representation is arranged with a predetermined forward succession sequence;implicitly generating a TTSSA trace tree from the trace code representation; andtransforming the trace code representation into native machine code by compiling the trace code representation in reverse of the predetermined forward succession sequence.