The following prior applications are herein incorporated by reference in their entirety for all purposes:
U.S. Patent Publication US-2017-0309346-A1 of application Ser. No. 15/494,435, filed Apr. 21, 2017, naming Armin Tajalli, entitled “Calibration Apparatus and Method for Sampler with Adjustable High Frequency Gain”, hereinafter identified as [Tajalli I].
U.S. Pat. No. 10,200,218 of application Ser. No. 15/792,696 filed Oct. 24, 2017, naming Armin Tajalli, entitled “Cascaded Sampler with Increased Wideband Gain”, hereinafter identified as [Tajalli II].
The present invention relates to communications systems circuits generally, and more particularly to the adjustment and control of circuits that instantaneously obtain an amplitude measurement of an input signal, relative to a provided reference signal level and clock.
In modern digital systems, digital information has to be processed in a reliable and efficient way. In this context, digital information is to be understood as information available in discrete, i.e., discontinuous values. Bits, collection of bits, but also numbers from a finite set can be used to represent digital information.
In most chip-to-chip, or device-to-device communication systems, communication takes place over a plurality of wires to increase the aggregate bandwidth. A single or pair of these wires may be referred to as a channel or link and multiple channels create a communication bus between the electronic components. At the physical circuitry level, in chip-to-chip communication systems, buses are typically made of electrical conductors in the package between chips and motherboards, on printed circuit boards (“PCBs”) boards or in cables and connectors between PCBs. In high frequency applications, microstrip or stripline PCB traces may be used.
Common methods for transmitting signals over bus wires include single-ended and differential signaling methods. In applications requiring high speed communications, those methods can be further optimized in terms of power consumption and pin-efficiency, especially in high-speed communications. More recently, vector signaling methods have been proposed to further optimize the trade-offs between power consumption, pin efficiency and noise robustness of chip-to-chip communication systems. In those vector signaling systems, digital information at the transmitter is transformed into a different representation space in the form of a vector codeword that is chosen in order to optimize the power consumption, pin-efficiency and speed trade-offs based on the transmission channel properties and communication system design constraints. Herein, this process is referred to as “encoding”. The encoded codeword is communicated as a group of signals from the transmitter to one or more receivers. At a receiver, the received signals corresponding to the codeword are transformed back into the original digital information representation space. Herein, this process is referred to as “decoding”.
Regardless of the encoding method used, the received signals presented to the receiving device must be sampled (or their signal value otherwise recorded) at intervals best representing the original transmitted values, regardless of transmission channel delays, interference, and noise. This sampling may occur independently in the time domain (as examples, in the analog domain using a sample-and-hold circuit, or in the digital domain using a clocked latch) and in the amplitude domain, (as examples, using a comparator or slicer) or as a combined time and amplitude sampling operation, using a clocked comparator or sampler. The timing of this sampling or slicing operation is controlled by an associated Clock and Data Alignment (CDA) timing system, which determines the appropriate sample timing.
Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
Circuits performing timed signal amplitude measurements, commonly referred to as “samplers”, are known in the art. Combining the time-sampling behavior of analog sample-and-hold or digital latches with the amplitude comparison behavior of a digital comparator or slicer, they are a common element of Data Communications receivers, typically providing the interface between front-end analog signal processing, and back-end digital data handling.
Sampler circuits have been derived from analog signal comparators, clocked digital latches, and other mixed analog/digital circuit architectures, each such architectural variation having known benefits and limitations. One architecture in particular, the clocked dynamic integrator/sampler, has been recognized for its ability to enable high speed operation, while still drawing low supply current. Derived from the classic analog differential comparator as shown in [Tajalli I], the sampler operates dynamically, charging an internal circuit node under control of a clock signal, then discharging that node through the comparison circuit, providing a timed comparison of active and reference input signals at the moment of clock signal transition. One embodiment of a clocked dynamic sampler is described in [Tajalli II].
Although fast and drawing low power, the dynamic nature of these circuits may lead to drift and stability issues in a production environment. Although individual MOS transistors within a given integrated circuit may be matched closely, their absolute operational parameters, in particular gate threshold voltage, gain, and channel resistance, may vary considerably between die, as well as within a die over variations in temperature and supply voltage. These variations may result in differences in data detection accuracy between devices, and may also lead to degradation of data detection within a device over variations in operating conditions.
Embodiments are described to measure operational characteristics of samplers as part of a closed-loop control system to mitigate the effect of such variations. To minimize impact on the production data detection path, an independent static analog circuit is used as a measurement proxy for the dynamic production circuit's operational characteristics.
To reliably detect the data values transmitted over a communications system, a communications receiver must accurately measure its received signal value amplitudes at carefully selected times, typically at or near the center of that received signal's period of stability between transitions (i.e. once per receive unit interval, or UL) The source of the received signal may be derived from a single wire signal, or may be derived from a weighted linear combination of multiple wire signals, such as provided by a Multi Input Comparator or mixer (MIC) used to detect vector signaling codes.
In some embodiments, the value of the received signal is first captured at the selected time using a sample-and-hold or track-and-hold circuit, and then the resulting value is measured against one or more reference values using a known voltage comparator circuit. Alternatively, the analog level of the received signal may be measured against a reference voltage using a comparator or “slicer”, with the digital result captured by a clocked digital latch.
The optimum point at which the received signal is measured is commonly described as the “center of eye”, (referring to the well-known “eye diagram” of signal amplitude vs. clock intervals.) In the time dimension, the sampling point is typically determined by use of a local “receive clock” which is configured to occur at that desirable sampling time. Generation and ongoing control of such receive clock timing is well understood in the art, as Clock Data Alignment (CDA, also known as Clock Data Recovery or CDR) systems measure and incrementally adjust sample timing versus receive signal stability time to optimize sample timing.
Similarly, the optimum reference level for the received signal's amplitude comparison may be dynamically generated. Decision Feedback Equalization or DFE is one such technique used to improve signal detection capabilities in serial communication systems. It presumes that the transmission line characteristics of the communications channel between transmitter and receiver are imperfect, thus energy associated with previously transmitted bits may remain in the channel (for example, as reflections from impedance perturbations) to negatively impact reception of subsequent bits. A receiver's DFE system processes each bit detected in a past unit interval (UI) through a simulation of the communications channel to produce an estimate of that bit's influence on a subsequent unit interval. That estimate, herein called the “DFE correction”, may be subtracted from the received signal to compensate for the predicted inter-symbol interference. Alternative embodiments may perform the functionally equivalent operation of such subtraction, by measuring the received signal (e.g. using a differential comparator) at a reference voltage level derived from the DFE correction signal. Practical DFE systems apply DFE corrections derived from multiple previous unit intervals (herein individually described as “DFE factors”) to the received signal before detecting a data bit.
Circuits performing a combined amplitude/time measurement, commonly referred to as “samplers”, are also known in the art. Combining the time-sampling behavior of analog sample-and-hold or digital latches with the amplitude comparison behavior of a digital comparator or slicer, they are a common element of Data Communications receivers, typically providing the interface between front-end analog signal processing, and back-end digital data handling. Sampler circuits have been derived from analog signal comparators, clocked digital latches, and other mixed analog/digital circuit architectures, each such architectural variation having known benefits and limitations.
One sampler architecture in particular, the clocked dynamic integrator/sampler, has been recognized for its ability to enable high speed operation, while still drawing low supply current. Derived from the classic analog differential comparator as shown in [Tajalli I], the sampler operates dynamically, charging an internal circuit node under control of a clock signal, then discharging that node through the comparison circuit, providing a timed comparison of active and reference input signals at the moment of clock signal transition. One embodiment of a clocked dynamic sampler is described in [Tajalli II].
Although fast and drawing low power, the dynamic nature of these circuits may lead to drift and stability issues in a production environment. Although individual MOS transistors within a given integrated circuit may be matched closely, their absolute operational parameters, in particular gate threshold voltage, gain, and channel resistance, may vary considerably between die, as well as within a die over variations in temperature and supply voltage. These variations may result in differences in data detection accuracy between devices, and may also lead to degradation of data detection within a device over variations in operating conditions.
Embodiments are described to measure operational characteristics of samplers as part of a closed-loop control system to mitigate the effect of such variations. To minimize impact on the production data detection path, an independent static analog calibration circuit is used as a measurement proxy for the dynamic production circuit's operational characteristics.
When input clock Clk goes high, the charging path is interrupted, and discharge paths via two branches are enabled to reset the pair of output nodes prior to the subsequent sampling interval. As shown in
In some embodiments, the structure of the clocked data sampler may be reversed, in which the pair of output nodes are pre-charged according to the sampling clock, and subsequently discharged at varying rates according to the input signal Vin+ and Vin−. Latches connected to the differential output nodes Vout+ and Vout− may be used to convert the integrated signal into a latched digital output for either implementation.
The resulting differential result Vout is dependent not only on the input signals, but to some degree also on the gain of input transistors 130/131 and the channel characteristics of transistors 140, 141, 150, 151, which are known to vary with the integrated circuit process, current, and over time and temperature. Thus, an associated control generator will typically adjust control signals [b1, b2, bn], modifying the magnitude of the current when charging the pair of output nodes Vout+ and Vout− so as to obtain a consistent differential result.
In some scenarios, a sampler calibration may be performed by adjusting a current based a common-mode value, and then measuring the sampler performance to ensure the current provides a proper sampling interval. Such scenarios would provide a duplicate dynamic sampler as in
Alternatively, as described herein, a static analog calibration circuit is utilized as a measurement proxy for a dynamic circuit such as that of
Comparator 310 compares the PVT-dependent output voltage Vfb obtained from
In some embodiments, the adjustable current is adjusted until the PVT-dependent output voltage is equal to the PVT-dependent reference voltage, or within some predetermined threshold. In some embodiments, the reference branch circuit corresponds to a replica of a branch circuit in the static analog calibration circuit. In some such embodiments, the adjustable current is split between through two branch circuits of the static analog calibration circuit and has a magnitude that is twice the magnitude of the reference current.
In some embodiments, the method further includes enabling the static analog calibration circuit and the reference branch circuit via enabling transistors. In some such embodiments, the static analog calibration circuit and the reference branch circuit are enabled to calibrate the PVT-calibrated current. In some embodiments, the static analog calibration circuit and the reference branch circuit are enabled responsive to a change in temperature. In some embodiments, the static analog calibration circuit and the reference branch circuit are enabled at system startup. In some embodiments, the static analog calibration circuit and the reference branch circuit are enabled responsive to a change in common mode input voltage.
In some embodiments, the control signal includes a plurality of bits. Some embodiments may utilize a binary code control signal for enabling corresponding current sources having different sizes connected in parallel in the clocked data sampler. Alternative embodiments may utilize a thermometer code control signal for enabling corresponding equal-sized current sources connected in parallel in the clocked data sampler.
In some embodiments, the comparisons between the PVT-dependent output voltage and the PVT-dependent reference voltage are accumulated in an accumulator circuit. Such an accumulator circuit may be a digital accumulator configured to accumulate comparisons from the comparator 310 in a least-significant-bit (LSB) portion, while a most-significant-bit portion provides the multi-bit control signal. Alternative accumulation devices may also be used. In some embodiments, the comparisons between the PVT-dependent output voltage and the PVT-dependent reference voltage are generated using a chopper amplifier 310, as depicted in
In some embodiments, the method further includes obtaining the common mode voltage input via a resistor-capacitor (RC) network connected to an output of a variable gain amplifier (VGA), the resistor-capacitor network operating on an information signal processed by the clocked data sampler. Such an RC network may correspond to a low-pass filter.
Other embodiments of control signal generator 380 may incorporate finite state machines, software or firmware executing on an embedded processor, or dedicated hardware to perform the described generation, measurement, adjustment, and configuration operations. In some embodiments, control signal operations occur periodically. In some embodiments, some or all of the static analog calibration circuit and the reference branch circuit may be powered down or disabled between measurements to reduce overall power consumption. Some embodiments operate at initial system startup to measure and compensate for process-related circuit differences. Further embodiments operate during some portion of normal system operation to measure and compensate for PVT-related variations. Control signals and/or their corresponding adjustments may represent equal-sized changes encoded in a thermometer code, binary weighted adjustments represented in a binary or gray code, and/or other functional encodings.
Number | Name | Date | Kind |
---|---|---|---|
3636463 | Ongkiehong | Jan 1972 | A |
3824494 | Wilcox | Jul 1974 | A |
3939468 | Mastin | Feb 1976 | A |
4276543 | Miller et al. | Jun 1981 | A |
4774498 | Traa | Sep 1988 | A |
4897657 | Brubaker | Jan 1990 | A |
5017924 | Guiberteau et al. | May 1991 | A |
5459465 | Kagey | Oct 1995 | A |
5510736 | Van | Apr 1996 | A |
5748948 | Yu et al. | May 1998 | A |
5793254 | OConnor | Aug 1998 | A |
5945935 | Kusumoto et al. | Aug 1999 | A |
6226330 | Mansur | May 2001 | B1 |
6232908 | Nakaigawa | May 2001 | B1 |
6346907 | Dacy et al. | Feb 2002 | B1 |
6384758 | Michalski et al. | May 2002 | B1 |
6396329 | Zerbe | May 2002 | B1 |
6400302 | Amazeen et al. | Jun 2002 | B1 |
6462584 | Proebsting | Oct 2002 | B1 |
6563382 | Yang | May 2003 | B1 |
6624699 | Yin et al. | Sep 2003 | B2 |
6839587 | Yonce | Jan 2005 | B2 |
6879816 | Bult et al. | Apr 2005 | B2 |
6888483 | Mulder | May 2005 | B2 |
6972701 | Jansson | Dec 2005 | B2 |
7075996 | Simon et al. | Jul 2006 | B2 |
7167523 | Mansur | Jan 2007 | B2 |
7188199 | Leung et al. | Mar 2007 | B2 |
7199728 | Dally et al. | Apr 2007 | B2 |
7269212 | Chau et al. | Sep 2007 | B1 |
7285977 | Kim | Oct 2007 | B2 |
7372295 | Wei | May 2008 | B1 |
7372390 | Yamada | May 2008 | B2 |
7397302 | Bardsley et al. | Jul 2008 | B2 |
7528758 | Ishii | May 2009 | B2 |
7656321 | Wang | Feb 2010 | B2 |
7683720 | Yehui et al. | Mar 2010 | B1 |
7688102 | Bae et al. | Mar 2010 | B2 |
7697915 | Behzad et al. | Apr 2010 | B2 |
7804361 | Lim et al. | Sep 2010 | B2 |
7957472 | Wu et al. | Jun 2011 | B2 |
8000664 | Khorram | Aug 2011 | B2 |
8030999 | Chatterjee et al. | Oct 2011 | B2 |
8106806 | Toyomura et al. | Jan 2012 | B2 |
8159375 | Abbasfar | Apr 2012 | B2 |
8159376 | Abbasfar | Apr 2012 | B2 |
8183930 | Kawakami et al. | May 2012 | B2 |
8547272 | Nestler et al. | Oct 2013 | B2 |
8581824 | Baek et al. | Nov 2013 | B2 |
8604879 | Mourant et al. | Dec 2013 | B2 |
8643437 | Chiu et al. | Feb 2014 | B2 |
8674861 | Matsuno et al. | Mar 2014 | B2 |
8687968 | Nosaka et al. | Apr 2014 | B2 |
8791735 | Shibasaki | Jul 2014 | B1 |
8841936 | Nakamura | Sep 2014 | B2 |
8860590 | Yamagata et al. | Oct 2014 | B2 |
9069995 | Cronie | Jun 2015 | B1 |
9106465 | Walter | Aug 2015 | B2 |
9148087 | Tajalli | Sep 2015 | B1 |
9178503 | Hsieh | Nov 2015 | B2 |
9281785 | Sjöland | Mar 2016 | B2 |
9292716 | Winoto et al. | Mar 2016 | B2 |
9300503 | Holden et al. | Mar 2016 | B1 |
10003315 | Tajalli | Jun 2018 | B2 |
10200218 | Tajalli | Feb 2019 | B2 |
10326623 | Tajalli | Jun 2019 | B1 |
20010006538 | Simon et al. | Jul 2001 | A1 |
20020050861 | Nguyen et al. | May 2002 | A1 |
20020149508 | Hamashita | Oct 2002 | A1 |
20020158789 | Yoshioka et al. | Oct 2002 | A1 |
20020174373 | Chang | Nov 2002 | A1 |
20030016763 | Doi et al. | Jan 2003 | A1 |
20030085763 | Schrodinger et al. | May 2003 | A1 |
20030132791 | Hsieh | Jul 2003 | A1 |
20030160749 | Tsuchi | Aug 2003 | A1 |
20030174023 | Miyasita | Sep 2003 | A1 |
20030184459 | Engl | Oct 2003 | A1 |
20030218558 | Mulder | Nov 2003 | A1 |
20040027185 | Fiedler | Feb 2004 | A1 |
20040169529 | Afghani et al. | Sep 2004 | A1 |
20050057379 | Jansson | Mar 2005 | A1 |
20050270098 | Zhang et al. | Dec 2005 | A1 |
20060036668 | Jaussi et al. | Feb 2006 | A1 |
20060097786 | Su et al. | May 2006 | A1 |
20060103463 | Lee et al. | May 2006 | A1 |
20060192598 | Baird et al. | Aug 2006 | A1 |
20060194598 | Kim et al. | Aug 2006 | A1 |
20070009018 | Wang | Jan 2007 | A1 |
20070176708 | Otsuka et al. | Aug 2007 | A1 |
20070182487 | Ozasa et al. | Aug 2007 | A1 |
20070188367 | Yamada | Aug 2007 | A1 |
20070201546 | Lee | Aug 2007 | A1 |
20080001626 | Bae et al. | Jan 2008 | A1 |
20080165841 | Wall et al. | Jul 2008 | A1 |
20080187037 | Bulzacchelli et al. | Aug 2008 | A1 |
20090090333 | Spadafora et al. | Apr 2009 | A1 |
20090115523 | Akizuki et al. | May 2009 | A1 |
20090323864 | Tired | Dec 2009 | A1 |
20100148819 | Bae et al. | Jun 2010 | A1 |
20100156691 | Taft | Jun 2010 | A1 |
20100219781 | Kuwamura | Sep 2010 | A1 |
20100235673 | Abbasfar | Sep 2010 | A1 |
20100271107 | Tran et al. | Oct 2010 | A1 |
20110028089 | Komori | Feb 2011 | A1 |
20110032977 | Hsiao et al. | Feb 2011 | A1 |
20110051854 | Kizer et al. | Mar 2011 | A1 |
20110057727 | Cranford et al. | Mar 2011 | A1 |
20110096054 | Cho et al. | Apr 2011 | A1 |
20110103508 | Mu et al. | May 2011 | A1 |
20110133816 | Wu et al. | Jun 2011 | A1 |
20110156819 | Kim et al. | Jun 2011 | A1 |
20120025911 | Zhao et al. | Feb 2012 | A1 |
20120044021 | Yeh et al. | Feb 2012 | A1 |
20120133438 | Tsuchi et al. | May 2012 | A1 |
20130106513 | Cyrusian et al. | May 2013 | A1 |
20130114663 | Ding et al. | May 2013 | A1 |
20130147553 | Iwamoto | Jun 2013 | A1 |
20130195155 | Pan et al. | Aug 2013 | A1 |
20130215954 | Beukema et al. | Aug 2013 | A1 |
20130259113 | Kumar | Oct 2013 | A1 |
20130334985 | Kim et al. | Dec 2013 | A1 |
20140119479 | Tajalli | May 2014 | A1 |
20140176354 | Yang | Jun 2014 | A1 |
20140177696 | Hwang | Jun 2014 | A1 |
20140203794 | Pietri et al. | Jul 2014 | A1 |
20140266440 | Itagaki et al. | Sep 2014 | A1 |
20140312876 | Hanson et al. | Oct 2014 | A1 |
20150070201 | Dedic et al. | Mar 2015 | A1 |
20150146771 | Walter | May 2015 | A1 |
20150198647 | Atwood et al. | Jul 2015 | A1 |
20160013954 | Shokrollahi et al. | Jan 2016 | A1 |
20160197747 | Ulrich et al. | Jul 2016 | A1 |
20170085239 | Yuan et al. | Mar 2017 | A1 |
20170104458 | Cohen et al. | Apr 2017 | A1 |
20170214374 | Tajalli | Jul 2017 | A1 |
20170309346 | Tajalli et al. | Oct 2017 | A1 |
20190199557 | Taylor et al. | Jun 2019 | A1 |
Number | Date | Country |
---|---|---|
2018052657 | Mar 2018 | WO |
Entry |
---|
Kim, Kyu-Young , et al., “8 mW 1.65-Gbps continuous-time equalizer with clock attenuation detection for digital display interface”, Analog Integrated Circuits and Signal Processing, Kluwer Academic Publishers, vol. 63, No. 2, Oct. 11, 2009, 329-337 (9 pages). |
Takahashi, Masayoshi , et al., “A 2-GHz Gain Equalizer for Analog Signal Transmission Using Feedforward Compensation by a Low-Pass Filter”, IEICE Transactions on Fundamentals of Electronics, vol. E94A, No. 2, Feb. 2011, 611-616 (6 pages). |
Wang, Hui , et al., “Equalization Techniques for High-Speed Serial Interconnect Transceivers”, Solid-State and Integrated-Circuit Technology, 9th International Conference on ICSICT, Piscataway, NJ, Oct. 20, 2008, 1-4 (4 pages). |
Anadigm , “Using the Anadigm Multiplier CAM”, Design Brief 208, www.anadigm.com, Copyright 2002, 2002, (6 pages). |
Schneider, J. , et al., ““ELEC301 Project: Building an Analog Computer””, http://www.clear.rice.edu/elec301/Projects99/anlgcomp/, Dec. 19, 1999, (9 pages). |
Tierney, J. , “A Digital Frequency Synthesizer”, Audio and Electroacoustics, IEEE Transactions, pp. 48-57, vol. 19, No. 1, Abstract, Mar. 1971, (1 page). |
Palmisano, G. , et al., “A Replica Biasing for Constant-Gain CMOS Open-Loop Amplifiers”, Circuits and Systems, IEEE International Symposium in Monterey, CA, May 31, 1998, 363-366 (4 pages). |