This application claims benefit of priority to Indian Application No. 201711042849, entitled “Dynamic Interrupt Rate Control In Computing Systems”, filed, Nov. 29, 2017, the entirety of which is incorporated herein by reference.
Modern processors include a variety of circuits and components to facilitate fast and efficient computation. In addition, circuits and components are included to manage communications between devices, including devices external to the processor. For example, input/output (I/O) controllers are generally included to manage communications with external devices such as display devices, external storage devices, network communications, as well as various other peripheral devices. In order to communicate with these devices, transactions are conveyed from, and received by, processing elements of the processor (e.g., central processing units, graphics processing units, etc.).
In recent years, greater effort has been put into reducing the power consumed by computing devices. In the case of battery operated computing devices, reducing power consumption can mean longer operating times before the battery must be recharged. In other cases, reducing power consumption may serve other purposes—such as reducing the operating temperature of a device or seeking to be more environmentally friendly. Whatever the reason, one of the drawbacks of reducing power consumption is that the performance of the device is typically reduced as well. If the performance of a device (e.g., a laptop, mobile phone, gaming console, etc.) is noticeably degraded due to mechanisms within the device to reduce power consumption, users become frustrated and dissatisfied with the device. As a consequence, users may not purchase the device.
In order to provide products that meet user's performance expectations, designers must balance power consumption concerns with performance issues. To this end, designers must determine when, and to what degree, a device can enter a reduced power state. One important component in the management of power consumption in a computing system is the time that a processing unit (such as a central processing unit, CPU) is in an idle state. Because CPUs consume relatively significant amounts of power when not idle, keeping the CPU in an idle state for longer periods of time can reduce power consumption. One activity that interferes with the idle state of a CPU is the handling of interrupts. Interrupts occur in response to activity detected by the system (e.g., I/O). For example, if a user activates an input device, such as a mouse, the activity is detected and an interrupt is generated. An interrupt handler then “interrupts” the CPU to let it know that activity has been detected that must be handled. In response to the interrupt, the CPU takes an action to respond to the activity—such as by causing a mouse pointer to move to a location on a display device, etc. When handling such interrupts, the CPU must exit an idle state (if it was in an idle state) to enter a higher power-performance state (power state). This higher power-performance state consumes more power than the idle state. When interrupts are handled as they come in, the CPU may be caused to enter and exit an idle state repeatedly which in turn reduces the effectiveness of the idle state on reducing power consumption.
While the immediate handling of interrupts as described above provides for improved performance, it increases power consumption. While this may be the most straightforward way of ensuring the performance of a device remains high, in some cases the immediate handling of interrupts may not be necessary for maintaining a satisfying user experience. In view of the above, system and methods are desired for enabling more efficient power management are desired.
The advantages of the methods and mechanisms described herein may be better understood by referring to the following description in conjunction with the accompanying drawings, in which:
In the following description, numerous specific details are set forth to provide a thorough understanding of the methods and mechanisms presented herein. However, one having ordinary skill in the art should recognize that the various embodiments may be practiced without these specific details. In some instances, well-known structures, components, signals, computer program instructions, and techniques have not been shown in detail to avoid obscuring the approaches described herein. It will be appreciated that for simplicity and clarity of illustration, elements shown in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements.
Various systems, apparatuses, and methods for masking and unmasking interrupts in a computing system are disclosed herein. Interrupts that are masked have their servicing intentionally delayed and are coalesced for a period of time during which they are not handled. At a later point in time, interrupts that have been coalesced are serviced.
In the embodiment shown, the CPU 102 is coupled to communicate with the interrupt controller 108 via a communication fabric 104. Communication fabric 104 is representative of any bus, crossbar, network, or other mechanism to convey data between the CPU 102 and the link controller 108. In various embodiments, the communication fabric 104 includes separate command and data paths. In other embodiments, a single path is used for conveyance of both commands and data.
Also shown in
In addition to the above,
As shown, three distinct power-performance levels are shown—Active, Idle S1, and Idle S2. While only three power-performance levels are shown, other embodiments can include more or fewer than three power-performance levels. Generally speaking, the “Active” level corresponds to a full power level and all components are on (All On). In other words, the component is not operating in a reduced power state. The “Idle S1” state represents a state in which the component is idle and has been idle for less than a threshold amount of time and is operating in a reduced power state. In this example, the display remains on, processor cores are in a low power state, and the I/O subsystem is in a low power state. The “Idle S2” state represents a state in which the component is idle and has been in an idle state for more than the threshold amount of time. While in the Idle S2 state the component is operating in a lower power state than when in the Idle S1 state. In this example, the display is turned off (Display Off) and the I/O subsystem is placed into an even lower power state.
Associated with each of the power-performance states are different interrupt handling modes. As shown in
In
As shown by the table 300, while in the Idle S1 state, interrupt masking is enabled (Masking On) and a duration of time T is set equal to some value N. N can be a number of cycles, or any other desired measure of time. As masking is enabled, interrupts that can be masked (intentionally delayed) are identified. In the example shown, interrupts of type A and type B are maskable, where A and B are designations representing two types or categories of interrupts that can occur in the system. This means that if an interrupt of type A or type B would ordinarily occur, servicing of these interrupts can be delayed (or “coalesced”). In various embodiments, coalescing interrupts includes storing data indicative of the interrupt (e.g., interrupt type, device ID, etc.) in a queue or other storage structure. When an interrupt is coalesced in this manner, the CPU is not made aware of the interrupt. Consequently, the CPU remains in its current idle state instead of transitioning to an Active state.
When masking is enabled as in row 312, the duration of time T effectively sets a limit on how long interrupts can be intentionally delayed/coalesced. For example, in one embodiment, while in Interrupt Mode 1, the masking duration T is set to some value N representing a given amount of time. Assuming only maskable interrupts are received during such a period of time, the received interrupts will be coalesced until the expiration of the time period T. When the time period T expires, any interrupts that have been coalesced are serviced. Servicing the interrupts will cause the CPU to exit an idle state and enter an active state. In the event there are no other conditions present that would keep the CPU in the Active state, the CPU can reenter the idle state after servicing the interrupts. If a non-maskable interrupt occurs while masking is enabled, the received non-maskable interrupt will be serviced without being coalesced and without regard to the masking duration T. In various embodiments, when the non-maskable interrupt is serviced, any other interrupts that were coalesced are also serviced at this time. Non-maskable interrupts can include interrupts associated with a user presence detection device (e.g., a camera), USB I/O devices (e.g., a mouse, pen, touch pad, etc.), or otherwise.
Returning to table 300, row 314 corresponds to an Idle S2 state. While in the Idle S2 state, Interrupt Mode 2 is in effect. When in Interrupt Mode 2, masking is enabled and a masking duration T is set. In this case, the duration T is set to some value M, where M>N. In effect, when the power-performance state is lower (as it is for Idle S2 as compared to Idle S1), then masking can be used more aggressively. In addition to having a longer masking duration, more and/or different types of interrupts can be maskable. In this example, two additional types of interrupts have been identified as being maskable so that interrupts of Type A, Type B, Type C, and Type D are all maskable, where A, B, C and D are designations representing different types or categories of interrupts that can occur in the system. Similar to that discussed above, interrupts identified as maskable will be coalesced until expiration of the maskable duration. Upon expiration of this period time, any coalesced interrupts will be serviced. Also, as above, if a non-maskable interrupt is received it will be serviced without coalescing and any interrupts that were coalesced can also be serviced.
Row 316 corresponds to an even lower power-performance state (Idle S3). In this state, Interrupt Mode 3 is in effect and masking of maskable interrupts is performed without a particular duration being established. In this case, interrupts will be masked until a non-maskable interrupt is received.
Turning now to
As shown in
If the current power state is not the Active state (404), but is the power state S1 (406), then a determination is made as to whether the received interrupt corresponds to a particular type of interrupt (416). In various embodiments, power state S1 represents a power state that is lower than the Active state, but higher than other power states of the system. In the embodiment shown, the particular type of interrupt (416) is one of type A or B, where A and B are designations representing two types or categories of interrupts that can occur in the system. If the interrupt does not correspond to the designated type (A or B) (416), then the received interrupt is not currently maskable and the received interrupt is serviced without the introduction of any intentional delays (420). However, if the received interrupt does correspond to one of the designated types (416), the servicing of the interrupt is intentionally delayed according to a given delay mode (Mode 1). Further details of the handling of interrupts for various delay modes is discussed in relation to
If the current power state is not S1 (406) but is state S2 (408), then a determination is made (412) as to whether the interrupt corresponds to at least one of multiple types including types A, B, C or D. In various embodiments, power state S2 represents a power state that is lower than the state S1, but higher than one or more other power states of the system. When in power state S2, more and/or different interrupt types can be deemed maskable. Hence, in the example shown, the categories have been expanded from types A and B (as shown in block 416) to also include types C and D (as shown in block 412). It is noted that while the discussion describes two types A and B in the first instance, and four types A, B, C, and D in the second instance, this is intended to be exemplary only. In various embodiments, any number of desired interrupts or types of interrupts can be included in each of the various groupings. For purposes of discussion, the designated types of interrupts in
If in block 412 the received interrupt does not correspond to one of the types A, B, C, or D, then the received interrupt is serviced without the introduction of any intentional delays 424. However, if the received interrupt corresponds to one of the designated types 412, then servicing of the interrupt is intentionally delayed according to a given delay mode (Mode 2).
Finally, if the current power state is not S2 (block 408), but is state S3 (a power state lower than S2) (410), then a determination is made as to whether the received interrupt corresponds to one of multiple types 414. In the example shown, the types illustrated in block 414 are the same as those in block 412. However, this need not be the case. In other embodiments, the types in block 414 can include additional and/or other types. If the received interrupt does not correspond to one of the designated types, then the interrupt is serviced without the introduction of an intentional delay 424. However, if the received interrupt does correspond to one of the designated types, then the interrupt is serviced according to a delayed servicing mode—Mode 3. In the example of
If in block 502 it is determined that the timer is currently active when the maskable interrupt is received, then the method foregoes setting the duration (i.e., skips block 504) and proceeds to block 506 where it waits for expiration of the timer or receipt of a non-maskable interrupt as described above. In such case, the intentional delay for the most recently received maskable interrupt will not be the full duration of N (assuming some time has already passed since the timer was set).
Servicing mode 2 (520) functions similar to that of servicing mode 1 (500), with the exception of which interrupts are deemed maskable and the duration of the intentional delay. As with servicing mode 1 (500), a determination is made as to whether the timer is already set and is active (522). If not, the timer is set to a value M wherein M is greater than N (524). In other words, the intentional delay for maskable interrupts in servicing mode 2 is longer than for servicing mode 1. The method then proceeds to block 526 where it waits for expiration of the timer or receipt of a non-maskable interrupt. When such an event occurs, servicing of the interrupts is allowed to proceed (528). If such an event has not yet occurred (526), masking of interrupts continues (530).
While in servicing mode 3 (540), interrupts are masked and their servicing is intentionally delayed until the system exits the current power state or a non-maskable interrupt is received (542). In this example, the current power state is a sleep state in which the processor is non-operational (i.e., is not currently powered to perform work). In this example, there is no timer used to stop the intentional delay of maskable interrupts. Consequently, servicing of maskable interrupts could be delayed for a significantly longer period of time than that of servicing mode 1 (500) or servicing mode 2 (520), assuming the system is not awakened and a non-maskable interrupt is not received. Assuming the system is not awakened and a non-maskable interrupt is not received, masking of interrupts continues (544). Otherwise, servicing of interrupts will be allowed to proceed (546).
While not illustrated in
In various embodiments, program instructions of a software application are used to implement the methods and/or mechanisms described herein. For example, program instructions executable by a general or special purpose processor are contemplated. In various embodiments, such program instructions can be represented by a high level programming language. In other embodiments, the program instructions can be compiled from a high level programming language to a binary, intermediate, or other form. Alternatively, program instructions can be written that describe the behavior or design of hardware. Such program instructions can be represented by a high-level programming language, such as C Alternatively, a hardware design language (HDL) such as Verilog can be used. In various embodiments, the program instructions are stored on any of a variety of non-transitory computer readable storage mediums. The storage medium is accessible by a computing system during use to provide the program instructions to the computing system for program execution. Generally speaking, such a computing system includes at least one or more memories and one or more processors that execute program instructions.
Although the embodiments above have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
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