Patent Application
20240146005
The technology of the disclosure relates generally to using lanes in a communication bus based on bandwidth needs.
Computing devices abound in modern society. Increased processing capabilities in such devices means that the devices have evolved into sophisticated computing and entertainment centers, thus enabling enhanced user experiences. With the advent of the myriad functions available to such devices, there has been increased pressure to find ways to move data from one integrated circuit to another or from one device to another. The Universal Serial Bus (USB) standard promulgated by the USB Implementers Forum (USB-IF) is one popular standard used by many market participants. The first USB standard was published in 1996. Since that time, USB 2.0, USB 3.0, and most recently, USB 4.0 have all been released. Since the August 2019 release of USB 4.0, a second version (v. 2.0) has been proposed and released as of Oct. 25, 2022. The evolution of the USB standard provides opportunities for innovation.
Aspects disclosed in the detailed description include dynamic lane reallocation based on bandwidth needs. In particular, exemplary aspects of the present disclosure allow for dynamic repurposing of low-speed lanes for creation of a high-speed lane on a communication bus. The repurposed low-speed lanes may be used to support a symmetrical high-speed link or an asymmetrical high-speed link. Further changes are provided to shield conductors in a cable to assist in preventing crosstalk or unwanted electromagnetic emissions. The addition of such a dynamic high-speed lane may assist in data transfer for data intensive use cases.
In this regard in one aspect, a cable is disclosed. The cable includes a first plug. The first plug includes twenty-two pins complying with a USB Type-C pin layout, a twenty-third pin corresponding to a B6 position, and a twenty-fourth pin corresponding to a B7 position. The cable also includes a second plug. The cable also includes a first conductor coupled to the twenty-third pin of the first plug. The cable also includes a second conductor coupled to the twenty-fourth pin of the first plug.
In another aspect, an endpoint is disclosed. The endpoint includes a receptacle configured to be connected to a plug on a cable, the receptacle complying with a USB Type-C pin layout. The endpoint also includes a physical interface (PHY). The PHY includes a control circuit. The control circuit is configured to send a first signal through an A6 pin and an A7 pin in the receptacle. The control circuit is also configured to concurrently send a second signal through a B6 pin and a B7 pin in the receptacle.
In another aspect, a method of dynamically reallocating lanes in a communication bus is disclosed. The method includes determining a need for a bandwidth. The method also includes assigning a USB 2.0 channel to handle a forty gigabits per second (40 Gbps) signal.
With reference now to the drawing figures, several exemplary aspects of the present disclosure are described. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Aspects disclosed in the detailed description include dynamic lane reallocation based on bandwidth needs. In particular, exemplary aspects of the present disclosure allow for dynamic repurposing of low-speed lanes for creation of a high-speed lane on a communication bus. The repurposed low-speed lanes may be used to support a symmetrical high-speed link or an asymmetrical high-speed link. Further changes are provided to shield conductors in a cable to assist in preventing crosstalk or unwanted electromagnetic emissions. The addition of such a dynamic high-speed lane may assist in data transfer for data intensive use cases.
Exemplary aspects of the present disclosure are well suited for use with a communication bus based on the Universal Serial Bus (USB) 4.0, version 2.0. Accordingly, the examples provided throughout the present disclosure are based thereon. However, it should be appreciated that other communication buses may benefit from the teachings set forth herein and the concepts are not limited to the USB environment. Likewise, future generations of USB may also benefit from the teachings presented herein.
To assist in understanding how to dynamically reallocate lanes based on bandwidth needs, a discussion of a USB 4.0 system is provided with reference to
In this regard,
The cables 106, 110, 114, and 118 may be integral to the device (e.g., the mouse end of the cable 118 may be integrated into the mouse 116) or have removable ends or plugs that plug into complementary receptacles as is well known. Aspects of the present disclosure apply to cables having two plugs or a plug and an integral end as well as USB buses that do not have a specific cable, but do have conductors operating according to a USB specification. It should be appreciated that the devices on either end of a cable may be referred to as endpoints. Likewise, in USB terminology, the host/master endpoint may be referred to as a downstream-facing port, and the slave/remote device endpoint may be referred to as an upstream-facing port.
One of the perceived complaints about early generations of USB was that plugs had a specific direction for insertion into receptacles. The advent of the Type-C receptacle and plug created a new form factor, and addressed this complaint by creating a mirrored pin layout as seen by the receptacle 120 of
Conventional plugs 130, illustrated in
There are use cases where more than 160 Gbps may be desired. For example, supporting two display port adaptor ports with 64 Gbps of a Peripheral Component Interconnect Express (PCIE) or the like may require more than 160 Gbps. Current USB 4 v.2 does not support such high bandwidth requirements. Again, these bandwidths are approximate.
Exemplary aspects of the present disclosure provide at least one and potentially two additional high-speed lanes by dynamically repurposing the “unused” D+/D− channel and pins. This dynamic repurposing requires some hardware modifications at the devices and additional conductors in the cable as well as some additional communication between the endpoints to verify that both endpoints support the improved bandwidth options. These modifications are set forth below.
In this regard, as illustrated in
In some aspects, the endpoints may not use any USB 2.0 channel thereby freeing up the original D+/D− lines. Thus, in receptacle 300 illustrated in
There may be multiple ways that endpoints may determine when and how to use the extra bandwidth afforded by aspects of the present disclosure. Two such processes are illustrated in
In this regard,
The downstream-facing port (i.e., the host or master) may then determine capability compatibility (block 406). This determination may be done in a variety of ways such as sending signals on the sideband channel, sending signals on the command and control (CC) channel, sending signals on the USB 2.0 channel, or the like. The signals may read from a register at the upstream-facing port (i.e., the slave or remote device) or the like.
The upstream-facing port may then determine if the USB 2.0 channel is used (block 408). While USB 4 assumes that the USB 2.0 channel will be used, not all use cases require such use. Thus, if the answer to block 408 is yes, the USB 2.0 channel is used, then pins B6 and B7 are used as a high-speed channel (block 410). However, if the answer to block 408 is no, the USB 2.0 channel is not used, then both sets of D+/D− pins may be used for high-speed channels (block 412).
The downstream-facing port may then allocate direction(s) for the high-speed channels based on need (block 414). For example, there could be 40 Gbps added in each direction raising the default value of 80 Gbps bidirectional to 120 Gbps bidirectional. Alternatively, it could be 160 Gbps in one direction and 80 Gbps in the other. Likewise, if only one additional high-speed channel is available, the split may be 120 Gbps in one direction and 80 Gbps in the other direction or 160 Gbps in one direction and 40 Gbps in the other. Other ratios may be used. In addition to setting the number of lanes, there may be a sequence (not illustrated) for enabling and synchronizing the lanes so that they can operate as part of the same link and data is synchronously distributed amongst them. A process for transitioning from symmetric to asymmetric lanes and the addition/removal of lanes is defined in the USB 4 2.0 specification and may be adjusted as appropriate for the additional dynamic lanes created by aspects of the present disclosure.
The downstream-facing port may also monitor to see if the need has changed (block 416). If yes, then the ratio may be reallocated at block 414. Otherwise, operation continues (block 418).
Another possibility, illustrated by process 420 in
In addition to the extra conductors in the cable to carry the additional channel, some changes may be made at the endpoints as better seen in
The communication buses with the ability to support dynamic lane and pin reallocation according to aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.
In this regard,
Other devices can be connected to the system bus 608. As illustrated in
The CPU(s) 602 may also be configured to access the display controller(s) 620 over the system bus 608 to control information sent to one or more displays 626. The display controller(s) 620 sends information to the display(s) 626 to be displayed via one or more video processors 628, which process the information to be displayed into a format suitable for the display(s) 626. The display(s) 626 can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.
Those of skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein may be implemented as electronic hardware, instructions stored in memory or in another computer readable medium wherein any such instructions are executed by a processor or other processing device, or combinations of both. The master devices, and slave devices described herein may be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and/or design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).
The aspects disclosed herein may be embodied in hardware and in instructions that are stored in hardware, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, base station, or server.
It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion. The operations described may be performed in numerous different sequences other than the illustrated sequences. Furthermore, operations described in a single operational step may actually be performed in a number of different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It is to be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications as will be readily apparent to one of skill in the art. Those of skill in the art will also understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Implementation examples are described in the following numbered clauses:
