Patent Application
20160327633
1. Field of the Disclosure
Embodiments of the present disclosure generally relate to Frequency Modulated Continuous Wave (FMCW) radar systems, and more specifically relate to dynamically programming chirps in FMCW radar systems.
2. Description of the Related Art
Frequency Modulated Continuous Wave (FMCW) automotive radar systems transmit and receive parameterized frequency-modulated signals commonly referred to as chirps. Typical applications of automotive radar systems require that the radar systems transmit a “burst” or sequence of chirps which may be referred to as a “frame” with minimal time gap between the chirps. A programmable digital timing engine configures the transmitted chirps. Typically, the parameter values of a chirp to be transmitted are written by a software program to a set of parameter registers in the timing engine. Due to software latency, chirp parameters may be fixed for a frame, i.e., the chirp parameters are programmed at the beginning of a frame and the timing engine configures each chirp in the frame using these parameters.
In some radar systems, there may be two sets of parameter registers. In such systems, the software may program both sets of registers to pre-configure two different types of chirps. The sequence of chirps transmitted during the frame is then selected based on the value of a counter. For example, the two pre-configured chirps may be transmitted in an alternating fashion based on the counter value being even or odd.
Embodiments of the present disclosure relate to methods and apparatus for dynamic programming of chirps in an FMCW radar system. In one aspect, a Frequency Modulated Continuous Wave (FMCW) radar system is provided that includes a chirp profile storage component configured to store a chirp profile for each chirp of a frame of chirps and a timing engine coupled to the chirp profile storage component to receive each chirp profile in transmission order during transmission of the frame of chirps, in which the timing engine uses each chirp profile to configure a corresponding chirp.
In one aspect, a method for programming chirps in a frame of chirps in a Frequency Modulated Continuous Wave (FMCW) radar system is provided that includes receiving a chirp profile for each chirp in the frame of chirps in a timing engine of the FMCW radar system in transmission order during transmission of the frame of chirps, in which each chirp profile is received from a chirp profile storage component in the FMCW radar system, and using, by the timing engine, each chirp profile to configure a corresponding chirp.
In one aspect, a Frequency Modulated Continuous Wave (FMCW) radar system is provided that includes a radar front end configured to transmit a frame of chirps in which each chirp in the frame of chirps is configured based on a chirp profile corresponding to the chirp, and in which each chirp in the frame of chirps has a separate corresponding chirp profile, and a processing unit coupled to the radar front end to provide the chirp profile for each chirp to the radar front end in transmission order.
Particular embodiments will now be described, by way of example only, and with reference to the accompanying drawings:
Specific embodiments of the disclosure will now be described in detail with reference to the accompanying figures. Like elements in the various figures are denoted by like reference numerals for consistency.
Multiple sequential chirps are typically transmitted in a unit referred to as a frame. As illustrated in
As previously mentioned, in some prior art radar systems, there are one or two sets of parameter registers that are programmed based on the desired chirp configurations. When there is one set of parameter registers, the same chirp configuration is used for all chirps in a frame. If there are two sets of parameter registers, two chirp configurations may be used in a frame based on the value of a counter.
In the prior art, chirp configurations such as these may be applied in different frames, which may result in losing important information about objects within view of the radar due to delays caused by using multiple frames to extract the needed information. Embodiments of the disclosure provide for using multiple chirp profiles in a single frame, which, with an appropriate combination of profiles, may reduce the time needed to extract object information. To accomplish this, chirp parameter registers used by the timing engine are configured in real time from chirp to chirp in a frame. In some embodiments, a chirp processing unit in the radar system, e.g., a field programmable gate array (FPGA) or a microcontroller (MCU), stores chirp timing parameters, i.e., a chirp profile, for each chirp in a frame of chirps. Further, the chirp processing unit transfers the chirp profile for each chirp to the timing engine in real time during transmission of the frame of chirps. Additional parameters, i.e., state configuration parameters, are also provided to the timing engine for configuring various components of the radar front end for transmission of the frame of chirps.
The processing unit 606 is coupled to the external memory 610 to receive radar signal data captured from the radar front end 604 during a frame. The processing unit 606 is also coupled to the chirp processing unit 602 to provide chirp profiles and state configuration parameters for the frame of chirps to be transmitted. Chirp profiles and state configuration parameters are explained in more detail below. The processing unit 606 is further coupled to the radar front end 604 to provide control information for the radar front end 604 other than chirp profiles. The processing unit 606 includes functionality to perform complex radar signal processing on radar signal data to determine, for example, distance, velocity, and angle of any detected objects. The processing unit 606 may also include functionality to perform post processing of information about the detected objects, such as tracking objects, determining rate and direction of movement, etc. The processing unit 606 may include any suitable processor or combination of processors as needed for the processing of collected radar data. For example, the processing unit 606 may include a digital signal processor (DSP), a microcontroller (MCU), an SOC combining both DSP and MCU processing, or a field programmable gate array (FPGA) and/or a DSP.
The processing unit 606 provides control information as needed to one or more electronic control units in the vehicle via the network interface 608. Electronic control unit (ECU) is a generic term for any embedded system in a vehicle that controls one or more the electrical system or subsystems in the vehicle. Types of ECU include, for example, electronic/engine control module (ECM), powertrain control module (PCM), transmission control module (TCM), brake control module (BCM or EBCM), central control module (CCM), central timing module (CTM), general electronic module (GEM), body control module (BCM), and suspension control module (SCM).
The network interface 608 may implement any suitable protocol, such as, for example, the controller area network (CAN) protocol, the FlexRay protocol, or Ethernet protocol. The external memory 610 may be any suitable memory design, such as, for example, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or double data rate DRAM (DDR DRAM), flash memory, a combination thereof, or the like.
The chirp processing unit 602 is configured to manage the sequence and type of chirps transmitted during a frame, including providing chirp profiles for each chirp in the frame to the radar front end 604 and capturing the radar signal data generated by the radar front end 604. The chip processing unit 602 may be implemented with any suitable processor, a hardware state machine, or a combination of thereof, as needed for real-time management of the chirp related data. For example, the chip processing unit 602 may be a field programmable gate array (FPGA), a microcontroller (MCU), a digital signal processor (DSP), a combination thereof, etc.
The chirp processing unit 602 includes a chirp profile storage component 612, a data capture component 614, and an external memory interface (EMIF) 616. The data capture component 614 includes functionality to capture radar signal data from the radar front end 604 during transmission of a frame of chirps and to store the data in the external memory 610. The EMIF 616 is coupled to the external memory 610 and may be used by the data capture component 614 to store the radar signal data captured during transmission of a frame in the external memory 610.
The chirp processing unit 602 includes functionality to receive chirp profiles for a frame of chirps and to store the chirp profiles in the chirp profile storage component 612. The chirp profile storage component 612 may be any suitable memory design, e.g., registers or the like. The amount of storage provided in the chirp profile storage component 612 is implementation dependent, and may be based on factors such as the maximum chirp frame size, i.e., the maximum number of chirps in a frame, supported by the radar system 600 and the maximum amount of storage needed for a chirp profile.
The chirp processing unit 602 further includes functionality to provide chirp profiles to the timing engine in the radar front end 604 in a round robin fashion. More specifically, the radar front end 604 includes chirp profile buffers, e.g., registers, for storing parameters of chirps to be transmitted. A chirp profile buffer stores parameters for a single chirp. Further, a chirp profile is a set of chirp timing parameters for a single chirp. Chirp profiles are described in more detail below. The number of chirp profile buffers is implementation dependent, and may be based on factors such as the throughput of the chirp processing unit 602 in filling the buffers, the cost to implement the buffers, etc.
The timing engine includes functionality to read chirp parameters in a round robin fashion from the chirp profile buffers during transmission of a frame of chirps. That is, if there are two chirp profile buffers A and B, the timing engine reads chirp parameters from buffer A, the next chirp parameters from buffer B, the next chirp parameters from buffer A, and so on. If there are four chirp profile buffers A, B, C, and D, the timing engine reads chirp parameters from buffer A, the next chirp parameters from buffer B, the next chirp parameters from buffer C, the next chirp parameters from buffer D, the next chirp parameters from buffer A, etc.
The chirp processing unit 602 includes functionality to move chirp profiles from the chirp profile storage 612 to the chirp profile buffers in a round robin fashion during transmission of a frame of chirps. That is, if there are two chirp profile buffers A and B, while the timing engine reads a chirp profile from buffer A, the chirp processing unit 602 provides the next chirp profile to the timing engine for storage in buffer B and while the timing engine reads a chirp profile from buffer B, the chirp processing unit 602 provides the next chirp profile to the timing engine for storage in buffer A. This pattern is repeated until all chirps in the frame have been transmitted.
If there are four chirp profile buffers A, B, C, and D, the buffers may be preloaded with chirp parameters for each of the first four chirps in a frame. Then, while the timing engine reads a chirp profile from buffer B, the chirp processing unit 602 provides the fifth chirp profile to the timing engine for storage in buffer A and while the timing engine reads a chirp profile from buffer C, the chirp processing unit 602 provides the sixth chirp profile to the timing engine for storage in buffer B. Further, while the timing engine reads a chirp profile from buffer D, the chirp processing unit 602 provides the seventh chirp profile to the timing engine for storage in buffer C and while the timing engine reads a chirp profile from buffer A, the chirp processing unit 602 provides the eighth chirp profile to the timing engine for storage in buffer D. This pattern is repeated until all chirps in the frame have been transmitted.
Chirp profiles are now explained in more detail. A chirp profile is a set of timing parameters for the timing engine in the radar front end 604. The cycle time of a single chirp, which may be referred to as a micro-cycle or a chirp cycle herein, is divided into time intervals and the beginning of each time interval is set by a timing parameter. Further, the actions performed by the timing engine during each time interval, e.g., start chirp, start radar data sampling, stop radar data sampling, etc., are defined. The number of time intervals and the actions performed during an interval are implementation dependent. For simplicity of explanation, six time intervals with timing parameters T1, T2, T3, T4, T5, and T6 are assumed.
The timing parameter values for a chirp, i.e., the chirp profile, may be determined from the values of various chirp configuration parameters. The number and types of chirp configuration parameters is implementation dependent, i.e., depends on the particular architecture of the radar system 600. Example chirp configuration parameters include a transmitter enable parameter for indicating which transmitters are to be enabled for a chirp, a starting frequency parameter for specifying the initial frequency of a chirp, a ramp slope parameter for specifying the slope of the frequency ramp of a chirp, a parameter for specifying when the radar signal data is initially valid for a chirp, a parameter specifying the number of radar signal data samples to capture, a parameter specifying the time between chirps, frequency synthesizer configuration parameters, and transceiver configuration parameters.
The timing engine translates the timing parameter values for a chirp into multiple device register writes that control the actions to be taken during each time interval.
The parameter mapping component 1004 receives chirp profiles and state configuration parameters for each chirp in a frame and maps the parameter values to registers in buffers 1008 in a round robin fashion. State configuration parameters are provided by the processing unit 606 and may include, for example, transmit antenna select, receiver bandwidth, etc. The finite state machine 1006 reads the chirp profile buffers 1008 in a round robin fashion and outputs control signals that control the state of the transceiver (or transceivers) in the transceiver component 1012 and the synthesizer 1010. Reading and writing chirp profile buffers in a round robin fashion is previously explained herein.
The counter 1002, which is reset for each micro-cycle, is used by the finite state machine 1006 to initiate actions for each of the time intervals at times corresponding to the timing parameters in the chirp profile. The finite state machine 1006 is clocked by a high speed reference clock and the counter 1002 is incremented at each rising clock signal edge. The use of this counter is explained in more detail in reference to Table 1 and the example of
The example of
While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the disclosure as disclosed herein.
For example, embodiments have been described herein in which the processing unit and the chirp processing unit are separate processing units. One of ordinary skill in the art will understand embodiments in which a single processing unit may be used instead of separate processing units. That is, the chirp processing unit and the processing unit may be the same processing unit.
In another example, embodiments have been described herein in which the chirp processing unit also performs radar signal data capture. One of ordinary skill in the art will understand embodiments in which the data capture is performed elsewhere, e.g., by the processing unit.
In another example, one of ordinary skill in the art will understand embodiments in which the radar front end, the chirp processing unit, and the processing unit are integrated in a single chip.
In another example, embodiments have been described herein in which the timing engine services the chirp profile buffers in round robin order. One of ordinary skill in the art will understand embodiments in which, when there are more than two chirp profile buffers, the number and choice of buffers to be serviced and/or the order in which the buffers are serviced is programmable.
Certain terms are used throughout the description and the claims to refer to particular system components. As one skilled in the art will appreciate, components in radar systems may be referred to by different names and/or may be combined in ways not shown herein without departing from the described functionality. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” and derivatives thereof are intended to mean an indirect, direct, optical, and/or wireless electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, through an indirect electrical connection via other devices and connections, through an optical electrical connection, and/or through a wireless electrical connection, for example.
It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope of the disclosure.
