"A Built-In Hamming Code ECC Circuit for DRAM's", Furutani et al., IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 50-56. |
"Cost Analysis of On-Chip Error Control Coding for Fault Tolerant Dynamic RAMs", Jarwala et al., The Computer Society of the IEEE, Proceedings of the Seventeenth International Symposium on Fault-Tolerance Computing, Jul. 6-8, 1987, pp. 278-283. |
"Circuit Technologies for 16 Mb DRAMs", Mano et al., 1987 IEEE International Solid-State Circuits Conf., pp. 22-25. |
"Design of a Fault-Tolerant DRAM with New On-Chip ECC", P. Mazumder, Center for Research on High-Frequency Microelectronics Dept. of EE and Comp. Sci., University of Michigan pp. 2.4-1-2.4-8. |
"A Novel Fault-Tolerant Design of Testable Dynamic Random Access Memory", Mazumder et al., IEEE 1987, pp. 306-309. |
"Selector-Line Merged Build-In ECC Technique for DRAM's", J. Yamada, IEEE Journal of Solid-State Circuits, vol. SC-22-No. 5, Oct. 1987. |
"A 4-Mbit DRAM with 16-bit Concurrent ECC", Yamada et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988 pp. 20-25. |
"Single-Event Upset (SEU) In a DRAM with On-Chip Error Correction", Zoutendyk et al., IEEE Transactions on Nuclear Science, vol. NS-34, No. 6, Dec. 1987 pp. 1310-1316. |
"Internal Correction of Errors in a DRAM", NASA's Jet Propulsion Laboratory, NASA Tech Briefs, Dec. 1989, pp. 30-31. |