Patent Application
20240155835
This application claims the priority benefit of Taiwan application serial no. 111142755, filed on Nov. 9, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The present disclosure relates to a memory device and a manufacturing method thereof, and in particular to a dynamic random access memory (DRAM) and a manufacturing method thereof.
With the progress of technologies, various kinds of electronic products are designed to be light, thin and small. However, as the trend develops, the critical dimension of the DRAM is also gradually reduced, which leads to an increase in the contact resistance between the contact and the active area in the DRAM and causes reduction of reliability. Therefore, how to reduce the contact resistance between the contact and the active area and improve the reliability of DRAM will be a very important issue.
The present disclosure provides a dynamic random access memory (DRAM) and a manufacturing method thereof, which are able to reduce the contact resistance between the contact of a capacitor and the active area, as well as improve reliability.
A DRAM of the disclosure includes a substrate, a plurality of isolation structures, a plurality of bit line structures, and a contact. The substrate has an active area. The plurality of isolation structures are formed in the substrate to separate the active area. The bit line structures are arranged on the substrate, and each bit line structure at least includes a conductive structure, an insulating cover layer and a spacer. The insulating cover layer is arranged on the conductive structure. The spacer is arranged on the side wall of the conductive structure and the side wall of the insulating cover layer. The conductive structure is configured to be electrically connected to the active area. The contact is located between the bit line structures, and at least a part of the contact extends below the spacer of one of the plurality of bit line structures.
The manufacturing method of the DRAM of the present disclosure at least includes the following steps. A substrate having an active area is provided. A plurality of bit line structures are formed on the substrate. Each bit line structure at least includes a conductive structure, an insulating cover layer and a spacer. The insulating cover layer is disposed on the conductive structure, the spacer is disposed on the side wall of the conductive structure and the side wall of the insulating cover layer, and the conductive structure is configured to be electrically connected with the active area. A groove is formed between the adjacent bit line structures, and the groove exposes part of the active area. An oxidation process is performed so that the exposed active area is formed into an oxide layer. The oxide layer is removed so that the groove extends below the spacer to form a contact opening. A contact is formed in the contact opening.
Based on the above, the present disclosure is able to increase the area of the active area exposed by the contact opening by locally oxidizing the active area exposed by the contact opening and removing the formed oxide layer. In this way, the contact area between the contact and the active area formed subsequently in the contact opening may be increased, thereby reducing the contact resistance between the contact and the active area, and improving the reliability of DRAM.
The present disclosure will be described more comprehensively with reference to the drawings of the present embodiment. However, the present disclosure can also be embodied in various forms without being limited to the embodiments described herein. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. The same or similar symbols indicate the same or similar elements, and the following paragraphs will not repeat the same details.
The present embodiment provides a method for manufacturing a dynamic random access memory (DRAM). Referring to
In some embodiments, the substrate 110 may be a semiconductor substrate or a semiconductor on insulator (SOI) substrate. The semiconductor material in the semiconductor substrate or the SOI substrate may include elemental semiconductors, alloy semiconductors, or compound semiconductors. For example, elemental semiconductors may include silicon (Si) or germanium (Ge). Alloy semiconductors may include silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), and the like. The compound semiconductor may include a group III-V semiconductor material or a group II-VI semiconductor material, but the present disclosure is not limited thereto. In some embodiments, the substrate 110 may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N type, and the second conductivity type may be P type.
In some embodiments, the material of the isolation structure 112 in the substrate 110 is an insulating material. For example, the material of the isolation structure 112 may respectively include silicon oxide, silicon nitride, silicon oxynitride, and the like or a combination thereof, but the disclosure is not limited thereto. In addition, the method of forming the isolation structure 112 is, for example, forming a plurality of trenches (not shown) in the substrate 110 and then filling the insulating material. Next, a removal process is performed to remove the insulating material from the substrate 110 to form the isolation structure 112 with a flat top surface 112t, and the removal process may be a chemical mechanical polishing process (CMP) or an etch-back process, but the present disclosure is not limited thereto.
Next, a plurality of bit line structures 120 may be formed on the substrate 110, and each bit line structure 120 may at least include a conductive structure 122, an insulating cover layer 124, and a spacer 126. Further, the insulating cover layer 124 may be disposed on the conductive structure 122, the spacer 126 may be disposed on the side wall 122s of the conductive structure 122 and the side wall 124s of the insulating cover layer 124, and the conductive structure 122 may be configured to be electrically connected to the active area AA. On the other hand, one of the plurality of bit line structures 120 may further include an insulating layer 121, and the insulating layer 121 is located between the conductive structure 122 and the substrate 110, but the disclosure is not limited thereto.
The material of the conductive structure 122 may include doped or undoped polysilicon, metal materials (such as tungsten), for example, include a bit line contact structure 122a and a bit line 122b, and the material of the bit line contact structure 122a may be different from that of the bit line 122b. In some embodiments, the material of the bit line contact structure 122a is doped polysilicon, and the material of the bit line 122b is tungsten, but the disclosure is not limited thereto.
Moreover, the material of the insulating layer 121, the material of the insulating cover layer 124, and the material of the spacer for forming the spacer 126 respectively include, for example, silicon oxide, silicon nitride, silicon oxynitride, and the like or a combination thereof, but the present disclosure is not limited thereto.
As shown in
In some embodiments, the method of forming the above-mentioned layers is, for example, performing deposition on the substrate 110 through chemical vapor deposition (CVD), and then forming the layers through a suitable patterning process, but the present disclosure is not limited thereto.
In this embodiment, a groove 10 is formed between adjacent bit line structures 120, and the groove 10 may expose part of the active area AA, such as exposing the top surface At of the active area AA below the spacer 126, and the downward direction is, for example, a direction facing the substrate 110. On the other hand, the groove 10 may also expose part of the isolation structure 112, such as exposing the surface 112T of the isolation structure 112 outside the spacer 126, so that the surface 112T is lower than the top surface 112t, but the disclosure is not limited thereto.
In detail, the spacer material used to form the spacer 126c may be formed on the entire substrate 110 first, and then the horizontal part of the spacer material is removed by using an etching process (such as a wet etching process) to form the spacer 126c and the groove 10 that expose parts of the active area AA and the isolation structure 112, but the disclosure is not limited thereto.
Please refer to
Referring to
In an embodiment, the orthographic projection of the spacer 126 on the substrate 110 and the orthographic projection of the oxide layer 130 on the substrate 110 at least partially overlap each other. In other words, part of the oxide layer 130 may be formed below the spacer 126, but the present disclosure is not limited thereto.
In some embodiments, the side wall 130s of the oxide layer 130 may be substantially aligned with the side wall 126s of the spacer 126, and the surface 130t of the oxide layer 130 may be substantially aligned with the surface 112T of the isolation structure 112, but the present disclosure is not limited thereto.
Referring to
In some embodiments, a part of the contact opening 142 is located below the spacer 126c, so that the outer side wall of the active area AA located below the spacer 126 is retracted compared to the outer side wall of the spacer 126c. That is, the width W1 of the active area AA located below the spacer 126 is smaller than the width W2 of the spacer 126. Further, the width W1 may be the minimum width of the active area AA, and the width W2 may be the maximum width of the spacer 126. On the other hand, the contact opening 142 may expose part of the isolation structure 112, and the surface 112T of the isolation structure 112 at the bottom of the contact opening 142 is higher than the surface AU of the active area AA, so that the bottom surface of the contact opening 142 is in a step shape, but the present disclosure is not limited thereto.
In some embodiments, the contact opening 142 has a width 142a, a width 142b, and a width 142c, and the width 142a, the width 142b, and the width 142c are different from each other. The width 142c is closest to the substrate 110, for example, the width 142a is farthest from the substrate 110, and the width 142b is located between the width 142a and the width 142c. The width 142b may be greater than the width 142a and the width 142c, and the width 142a may be greater than the width 142c, but the disclosure is not limited thereto.
In an embodiment, the bottom of the contact opening 142 is located below the spacer 126 of the bit line structure 120 having the insulating layer 121, that is, the contact opening 142 extends below one of the plurality of bit line structures 120, but the present disclosure is not limited thereto.
Please refer to
The material of the second portion 140d of the contact 140 may be different from that of the first portion 140c, for example, the material of the second portion 140d may be tungsten. It should be noted that the present disclosure does not limit the conductive material to be filled with different conductive materials in batches, and in other embodiments that are not shown, a single conductive material may also be filled in the contact opening 142.
After the above process, the manufacture of the DRAM 100 of this embodiment may be substantially completed. The DRAM 100 includes a substrate 110, a plurality of bit line structures 120, and a contact 140. The substrate 110 has an active area AA. The plurality of bit line structures 120 are disposed on the substrate 110, and each bit line structure 120 at least includes a conductive structure 122, an insulating cover layer 124, and a spacer 126. The insulating cover layer 124 is disposed on the conductive structure 122. The spacer 126 is disposed on the side wall 122s of the conductive structure 122 and the side wall 124s of the insulating cover layer 124. The conductive structure 122 is configured to be electrically connected to the active area AA. The contact 140 is located between the plurality of bit line structures 120, and at least a portion of the contact 140 extends below the spacer 126 of one of the plurality of bit line structures 120. Accordingly, in this embodiment, part of the active area AA is formed into the oxide layer 130 by performing an oxidation process on the active area AA exposed by the contact opening 142, and then, the oxide layer 130 is removed to form the contact opening 142 extending below the spacer 126 of the bit line structure 120. In this manner, at least a portion of the contact 140 formed in the contact opening 142 may extend below the spacer 126 of the bit line structure 120, thus effectively improving the contact area between the contact 140 and the active area AA and reducing the contact resistance between the contact 140 and the active area AA, as well as improving the reliability of the DRAM. In addition, by performing the oxidation process, the depth and position of the contact opening may be controlled more precisely, but the disclosure is not limited thereto.
In some embodiments, the contact 140 may be embedded in the substrate 110, for example, the contact 140 may be embedded in the active area AA, and the contact 140 is directly in contact with the side wall 126s of the spacer 126 and at least a portion of the below of the spacer 126, but the present disclosure is not limited thereto.
In some embodiments, the edge 112e of the isolation structure 112 is located within the contact 140, in other words, the isolation structure 112 is in direct contact with the contact 140. In some embodiments, at least a portion of the contact 140 extends below the spacer 126 of one of the plurality of bit line structures 120 having the insulating layer 121. In some embodiments, the orthographic projection of the contact 140 on the substrate 110 and the orthographic projection of the spacer 126 on the substrate 110 at least partially overlap each other.
In some embodiments, a portion of the bit line structure 120 electrically connected to the active area AA may be regarded as a source, and the contact 140 may be electrically connected to the drain. On the other hand, the DRAM 100 may further have a gate (not shown) between the source and the drain, and the gate may be a buried gate, but the disclosure is not limited thereto. In addition, a capacitor 136 may be further disposed above the contact 140, so the contact 140 may be a capacitor contact. In detail, an interlayer dielectric layer 134 and a capacitor 136 located in the interlayer dielectric layer 134 may be formed. The capacitor 136 includes a lower electrode 136a, a capacitor dielectric layer 136b, and an upper electrode 136c. The structure of the capacitor 136 only serves as an example, and the disclosure is not limited thereto. The lower electrode 136a of the capacitor 136 is connected to the contact 140, so that the capacitor 136 may be electrically connected to the active area AA through the contact 140. Since the process of forming the interlayer dielectric layer 134 and the capacitor 136 is known to those skilled in the art, related description is omitted here.
In summary, the present disclosure forms an oxide layer by partially oxidizing the active area exposed by the contact opening, and then removes the aforementioned oxide layer to form a contact opening extending below the spacer of the bit line structure. As such, at least a portion of the contact formed in the contact opening subsequently may extend below the spacer of the bit line structure. In this way, the contact area between the contact and the active area may be effectively increased, the contact resistance between the contact and the active area may be reduced, and the reliability of the DRAM may be improved. The invention is suitable for producing miniaturized DRAMs to increase the total number of dies on the wafer. Therefore, the present invention can reduce the production cost and energy consumption of manufacturing a single IC, and reduce the production energy consumption of subsequent packaging, thereby reducing carbon emissions in the production process of DRAMs. Furthermore, since the reliability of the DRAM of the present invention is improved, the present invention provides a green semiconductor technology.
Accordingly, the present disclosure may be used on automotive electronics, such as Advanced Driver Assistance Systems (ADAS), Instrument Clusters, Infotainment. The present disclosure may be used on Industrial applications, such as aerospace, medical, safety equipment, health & fitness, industrial controls, instrumentation, security, transportation, telecommunications, PoS machines, human machine interface, programmable logic controller, smart meter, and industrial networking. The present disclosure may be used on communication and networking devices such as STB, switches, routers, passive optical networks, xDSL, wireless access point, cable modem, power line communications M2M, mobile phones, base stations, DECT phones, and many other new communication products. The present disclosure may be used on desktops, notebooks, servers, gaming notebooks, ultrabooks, tablets, convertibles, HDD, and SSD. The present disclosure may be used on space constrained applications including Wearable, MP3 players, smart watches, games, digital radio, toys, cameras, digital photo album, GPS, Bluetooth and WiFi modules. The present disclosure may be used on television, display and home electronics.
Although the present disclosure has been disclosed as above with embodiments, it is not intended to limit the present disclosure. Those with ordinary knowledge in the technical field may make some modifications and changes without departing from the spirit and scope of the present disclosure. Therefore, the scope to be protected by the present disclosure should be defined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 111142755 | Nov 2022 | TW | national |
