Claims
- 1. A structure for a dynamic random access memory integrated circuit device, comprising:
- a substrate having an upper surface;
- an isolation trench having two sides and a substantially flat bottom in the substrate, wherein the trench defines first and second substrate areas on either side thereof, and wherein the trench has a doped channel stop region in the substrate at the bottom thereof;
- first and second gate electrodes spaced from the trench over the first and second substrate areas, respectively;
- first and second bit line source/drain regions formed in the substrate upper surface adjacent the first and second gate electrodes, respectively, wherein the gate electrodes lie between the trench and the bit line source/drain regions;
- first and second capacitor source/drain regions formed in the substrate upper surface adjacent the first and second gate electrodes, respectively, and lying between the gate electrodes and contacting the sides of the trench, wherein the trench extends deeper below the substrate surface than do the capacitor source/drain regions;
- first and second bit line contacts to the first and second bit line source/drain regions, respectively;
- first and second tungsten plugs connected to the first and second capacitor source/drain regions, respectively, and extending substantially vertically above the first and second gate electrodes, respectively to form first and second lower capacitor plates;
- an insulating layer over the tungsten plugs and extending down into the trench; and
- a conductive layer over the insulating layer, forming an upper capacitor plate corresponding to the lower capacitor plates;
- wherein the lower capacitor plates, together with the upper capacitor plate, form charge storage capacitors for DRAMs.
- 2. The structure of claim 1, wherein the conductive layer comprises tungsten.
- 3. The structure of claim 1, wherein the insulating layer comprises titanium dioxide.
- 4. The structure of claim 1, further comprising:
- a region of insulating material filling the trench over the conductive layer.
Parent Case Info
This is a continuation of application Ser. No. 07/869,758, filed Apr. 16, 1992, which is a division of application Ser. No. 07/320,064 filed Mar. 6, 1989, now U.S. Pat. No. 5,143,861.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
1208256 |
Sep 1986 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Ohta et al., "Quadruply Self-Aligned Stacked High-Capacitance RAM Using Ta.sub.2 O.sub.5 High-Density VLSI Dynamic Memory", IEEE Transactions on Electron Devices, vol. ED. 29 No. 3, Mar. 1982. |
Koyanagi et al., "A 5-V Only 16-Kbit Stacked Capacitor MOSRAM", IEEE Transactions Electron Devices, vol. ED 27, No. 8, Aug. 1980. |
Divisions (1)
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Number |
Date |
Country |
Parent |
320064 |
Mar 1989 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
869758 |
Apr 1992 |
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