Claims
- 1. A circuit implementing an OR logic function with a first and second input signal, comprising:
- a first switching device having a gate receiving a reset signal, a source coupled to a supply line of the circuit, and a drain;
- a second switching device having a gate receiving said first input signal, a drain coupled to the drain of said first switching device at a first node, and a source, said first node providing an output signal;
- a third switching device having a gate receiving said second input signal, a drain coupled to said first node, and a source;
- a fourth switching device having a gate, a drain coupled to the source of said second switching device and to the source of said third switching device, and a source coupled to ground;
- a first logic gate having a first input receiving said output signal, a second input, and an output;
- a second logic gate having a first input coupled to the output of said first logic gate, a second input, and an output;
- an inverter coupling the gate of said fourth switching device to the output of said second logic gate and to the second input of said first logic gate;
- a third logic gate having a first input coupled to the first input signal, a second input coupled to said second input signal, and an output coupled to said second input of said second logic gate, whereby said output signal is active when either the first or second input signals are active.
- 2. The circuit of claim 1, wherein said first switching device is a p-channel MOSFET.
- 3. The circuit of claim 1, wherein said second, third and fourth switching devices are a n-channel MOSFETs.
- 4. The circuit of claim 1, wherein said first, second, and third logic gates are NOR gates.
- 5. The circuit of claim 1, further comprising a second inverter coupled from said first node to the output signal.
- 6. The circuit of claim 1, further comprising a second inverter coupled from said first node to a third inverter, said third inverter coupled to said first node.
- 7. A circuit implementing an AND logic function with a first and second input signal, comprising:
- a first switching device having a gate receiving a reset signal, a source coupled to a supply line of the circuit, and a drain;
- a second switching device having a gate receiving said first input signal, a drain coupled to the drain of said first switching device at a first node, and a source, said first node providing an output signal;
- a third switching device having a gate receiving said second input signal, a drain coupled to said source of the second switching device, and a source;
- a fourth switching device having a gate, a drain coupled to the source of said third switching device, and a source coupled to ground;
- a first logic gate having a first input coupled to said output signal, a second input, and an output;
- a second logic gate having a first input coupled to the output of said first logic gate, a second input, and an output;
- a first inverter coupling the gate of said fourth switching device to the output of said second logic gate and to the second input of said first logic gate;
- a second inverter coupling the first input signal to said second input of said second logic gate, whereby said output signal is active when the first input signal and the second input signals are active.
- 8. The circuit of claim 7, wherein said first switching device is a p-channel MOSFET.
- 9. The circuit of claim 7, wherein said second, third and fourth switching devices are n-channel MOSFETs.
- 10. The circuit of claim 7, wherein said first, and second logic gates are NOR gates.
- 11. The circuit of claim 7, further comprising a third inverter coupled from said first node to the output signal.
- 12. The circuit of claim 7, further comprising a third inverter coupled from said first node to a fourth inverter, said fourth inverter coupled to said first node.
Parent Case Info
This application is a division of application Ser. No. 09/037,251, filed Mar. 9, 1998 now U.S. Pat. No. 5,952,859.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5708374 |
Durham et al. |
Jan 1998 |
|
5760610 |
Naffziger |
Jun 1998 |
|
Divisions (1)
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Number |
Date |
Country |
Parent |
037251 |
Mar 1998 |
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