FIELD OF THE INVENTION
This invention relates to circuitry and, more particularly, to electrostatic discharge (ESD) protection circuitry.
BACKGROUND
FIG. 1 illustrates conventional signal output circuitry 100 having a signal output signal pad 102 that is coupled to an output signal node 107 of a High Voltage (HV) output buffer circuit 170 that includes HV complementary metal-oxide semiconductor (CMOS) driver circuitry coupled between positive high voltage supply rail VDDH and negative supply rail VSS (ground) as shown. Output buffer circuit 170 includes a HV P-channel MOSFET (PMOS) output transistor 110 and a HV N-channel MOSFET (NMOS) output transistor 112 that each have a gate coupled to an internal output control circuit 114. Signal pad 102 is coupled at node 107 between the HV PMOS output transistor 110 and the HV NMOS output transistor 112 of buffer circuit 170. As further illustrated, signal output circuitry 100 is configured with a high voltage electrostatic discharge (ESD) protection device that includes an N-channel insulated-gate bipolar transistor (NiGBT) device 180 that is coupled between signal pad 102 and ground or VSS at node 103 as shown to form an embedded parasitic silicon controlled rectifier (SCR). NiGBT device 180 includes a NMOS transistor M1, with a PNP bipolar transistor Q1 coupled as shown between signal pad 102 and ground. NMOS transistor M1 itself is coupled between the base of PNP transistor Q1 and ground, with a parasitic NPN transistor Q2 also coupled between the base of PNP transistor Q1 and ground. As shown, the gate of NMOS transistor M1 is also coupled to ground.
The occurrence of a positive ESD event 190 on signal pad 102 causes a corresponding rise in voltage of the drift region due to the forward biased emitter-base diode of PNP transistor Q1. This voltage appears across the entire N-type drift region which begins at the base of Q1 and terminates at the drain of M1. An effective drift resistance RDRIFT exists between these two points where the drift region is generally engineered to be very lightly doped. The ESD potential which was originally applied to signal pad 102 now appears across the drain body diode of M1 which is reverse biased. As the ESD potential continues to rise, eventually the drain-body diode of M1 will avalanche breakdown, thereby generating electron-hole pairs in the process. When the generated holes flow to ground through the substrate resistance RS, an elevation in substrate potential occurs that acts to forward bias the base-emitter junction of parasitic NPN Q2, thereby turning this device on which causes collector current to flow in Q2. The collector current in Q2 in turn causes base and collector current to flow in Q1. The collector current in Q1 acts to further elevate the potential across RS which causes a further increase in base and collector current in Q2. A positive feedback loop is formed and the parasitic SCR turns on and shunts the ESD current from signal pad 102 to ground. The voltage at which the parasitic SCR turns on is called VT1 and is set entirely here by the breakdown voltage of the drift region to body-diode of transistor M1. In general VT1 must be set higher than the normal operating voltage of the output buffer circuit 170 that NiGBT device 180 is protecting. Often times in high voltage processes, the VTI of the protection device is also very close in magnitude to the voltage at which the HV NMOS and HV PMOS output devices themselves are damaged and great care must be taken to ensure that the ESD device triggers before an output buffer device.
SUMMARY
Disclosed herein are circuit configurations and related methods that may be implemented using insulated-gate bipolar transistor (IGBT) device circuitry to protect at risk circuitry (e.g., such as high voltage output buffer circuitry or any other circuitry subject to undesirable ESD events) from damage due to ESD events. The ESD events described herein, occur during assembly of integrated circuits onto printed circuit boards and as such, occur when the chip is in an unpowered state. Using the disclosed circuitry and methods, the magnitude of the trigger voltage VT1 threshold for an IGBT ESD protection device may be dynamically controlled between at least two different values, e.g., a first low trigger voltage threshold and a second high trigger voltage threshold that is higher than the first low trigger voltage threshold. In this way, trigger voltage VT1 threshold for an IGBT ESD protection device may be selectively reduced to guarantee that it is significantly lower than the failure voltage of the devices that it is protecting.
In one exemplary embodiment, the disclosed circuitry and methods may be implemented to control the trigger voltage of an IGBT ESD protection device to be a lower trigger voltage threshold value that is less than or equal to the normal operating voltage of the protected circuitry during an unpowered condition of the at risk circuitry, e.g., so as to sufficiently protect the unpowered at risk circuitry from ESD events that may occur during circuit fabrication and system assembly. In this same embodiment, the disclosed circuitry and methods may be implemented to dynamically control the trigger voltage of the IGBT ESD protection device to be a higher trigger voltage threshold value that is greater than the normal operating voltage of the at risk circuitry during a powered condition, e.g., so as to prevent the normal operating voltage of the at risk circuitry from triggering the IGBT ESD protection device. The disclosed circuitry and methods may be implemented in one exemplary embodiment to protect high voltage at risk circuitry, e.g., such as signal output circuitry having a normal operating voltage that is less than about 150 volts and greater than or equal to about 50 volts.
In one respect, disclosed herein is a semiconductor circuit device, including: a signal pad; a first supply rail; an insulated-gate bipolar transistor (IGBT) device coupled to form an embedded parasitic silicon controlled rectifier (SCR) between the signal pad and the first supply rail; a resistor coupled in a first current path between a gate of the IGBT device and the first supply rail; a switching element coupled in a second current path between the gate of the IGBT device and the first supply rail, the second current path being parallel to the first current path; where the switching element is configured to selectively couple the gate of the IGBT device to the first supply rail through the second current path to lower a resistance to current flow between the gate of the IGBT device and the first supply rail.
In another respect, disclosed herein is a method, including: operating a semiconductor circuit device that includes an insulated-gate bipolar transistor (IGBT) device that is coupled to form an embedded parasitic silicon controlled rectifier (SCR) between a signal pad and a first supply rail of a circuit device, a resistor being coupled in a first current path between a gate of the IGBT device and the first supply rail, and a switching element being coupled in a second current path between the gate of the IGBT device and the first supply rail such that the second current path is parallel to the first current path; and using the switching element to selectively couple the gate of the IGBT device to the first supply rail through the second current path to lower a resistance to current flow between the gate of the IGBT device and the first supply rail.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates conventional high voltage signal output circuitry that includes an NiGBT ESD protection device.
FIG. 2 illustrates signal output circuitry 200 according to one exemplary embodiment of the disclosed circuitry and methods.
FIG. 3 illustrates a partial cross section of a silicon-on-insulator (SOI) device structure of a NiGBT circuit device according to one exemplary embodiment of the disclosed circuitry and methods.
FIG. 4 illustrates relationship between current and voltage according to one exemplary embodiment of the disclosed circuitry and methods.
DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
FIG. 2 illustrates signal output circuitry 200 according to one exemplary embodiment of the disclosed circuitry and methods. Signal output circuitry 200 may in one embodiment be a part of the integrated circuitry of an integrated subscriber line interface circuit (SLIC) chip or other silicon-on-insulator (SOI) integrated circuit, although the disclosed circuitry and methods may be implemented with other types of integrated circuitry as well. As shown in FIG. 2, circuitry 200 includes a signal output signal pad 202 that is coupled to an output signal node 207 of an output buffer circuit 270 that includes HV complementary metal-oxide semiconductor (CMOS) driver circuitry coupled between positive high voltage supply rail VDDH and VSS (ground) as shown. Output buffer circuit 270 includes a HV P-channel MOSFET
(PMOS) output transistor 210 and a HV N-channel MOSFET (NMOS) output transistor 212 that each have a gate coupled to an internal output control circuit 214. Signal pad 202 is coupled at node 207 between the HV PMOS output transistor 210 and the HV NMOS output transistor 212 of buffer circuit 270. As further illustrated, signal output circuitry 200 is configured with a high voltage electrostatic discharge (ESD) protection device that includes an N-channel insulated-gate bipolar transistor (NiGBT) circuit device 280 that is coupled between signal pad 202 and ground or VSS at node 203 as shown to form an embedded parasitic silicon controlled rectifier (SCR). NiGBT circuit device 280 includes a NMOS transistor M1, with a PNP bipolar transistor Q1 coupled as shown between signal pad 202 and ground. NMOS transistor M1 itself is coupled between the base of PNP transistor Q1 and ground, with a parasitic NPN transistor Q2 also coupled between base and of PNP transistor Q1 and ground to form the SCR. As shown, the gate of NMOS transistor M1 is also coupled to ground through series gate resistor RG that has a non-zero resistance (e.g., high value resistor such as about 20 kilo ohms in one exemplary embodiment).
Also shown in FIG. 2 is gate control circuit 295 that includes a gate coupling switch that is coupled in parallel with gate resistor RG between the gate of NMOS transistor M1 and ground, and that is configured to selectively close to short the gate of NiGBT NMOS transistor M1 to ground when signal output circuitry 200 is powered on. When the signal output circuitry 200 is powered off, the gate coupling switch is configured to remain open so that the only current path between ground and the gate of NiGBT NMOS transistor M1 is through gate resistor RG which operates to lower the trigger voltage of the NiGBT device 280 as described further herein. In the particular illustrated embodiment of FIG. 2, the gate coupling switch is an NMOS transistor M2 that has its gate coupled to positive low voltage supply rail VDDL of signal output circuitry 200 via resistor R1 (e.g., about 5K ohms in one exemplar embodiment) that may be present, for example, to reduce gate oxide stress during ESD events on the VDDL supply. It will be understood that in other embodiments a gate control circuit may be any other suitable type of switching element, e.g., such as PMOS transistor with inverter coupled between the gate of the PMOS transistor and positive low voltage supply rail VDDL of signal output circuitry 200, etc.
In one embodiment, high voltage supply rail VDDH may be present for purposes of supplying high voltage power from an external source to HV signal interface power-consuming circuitry of a chip on which signal output circuitry 200 is integrated, while low voltage supply rail VDDL may be present for purposes of supplying low voltage power from an external source to logic and control power-consuming circuitry of a chip on which signal output circuitry 200 is integrated. In this regard, it will be understood that high voltage supply rail VDDH may be operated at any voltage that is relatively higher than the voltage of low voltage supply rail VDDL. For example, in one exemplary embodiment, high voltage supply rail VDDH may be operated at a voltage of less than or equal to about 150 volts but greater than or equal to about 50 volts, and low voltage supply rail VDDL may be operated at a voltage of about 5 volts or less, although in other embodiments VDDH and VDDL may be operated at any other respective voltages such that VDDH is higher than a corresponding voltage of VDDL of the same embodiment.
However, high voltage supply rail VDDH may be operated at any other voltage that is relatively higher than a corresponding operating voltage of low voltage supply rail VDDL. For example, the disclosed circuitry and methods may be implemented in other embodiments for signal output circuitry having a normal operating voltage that is greater than about 140 volts, alternatively greater than about 130 volts, alternatively greater than about 120 volts, alternatively greater than about 110 volts, alternatively greater than about 100 volts, and further alternatively from about 100 volts to about 200 volts. However, it will be understood that the the disclosed circuitry and methods may be implemented in other embodiments for signal output circuitry having a normal operating voltage that is less than 100 volts or greater than 200 volts.
Still referring to FIG. 2, occurrence of a positive ESD event 190 on signal pad 202 causes a rise in voltage on the gate of NMOS transistor M1 due to capacitive coupling, the magnitude of which is determined in part by a capacitive voltage divider formed with the gate-to-drain capacitance (CGD) and the gate-to-source capacitance (CGS). An effective feedthrough ratio is thereby formed, where a fractional portion of the ESD potential appearing on pad 202 will appear between the gate and ground of NMOS transistor M1. In general the feedthrough ratio must be chosen to couple enough of the applied ESD potential onto the gate of M1 to form a channel but not too high of a potential as to cause gate oxide damage. At the critical ESD trigger voltage (VT1) on signal pad 202 which causes the ESD-induced voltage on the gate of NMOS transistor M1 to exceed its MOS-threshold voltage (VT), NMOS transistor M1 turns on to allow initial current flow from base of PNP transistor Q1 through drift region resistance RDRIFT to ground, which in turn causes PNP transistor Q1 to begin to conduct ESD event current from pad 202 to ground through source resistance (RS). Current conducted through PNP transistor Q1 also flows into base of parasitic NPN transistor Q2 causing NPN transistor Q2 to conduct current from base of PNP transistor Q1 through drift region resistance RDRIFT to ground. Thus a positive feedback loop is formed as before and the parasitic SCR is in a locked-on state. The parasitic SCR stays locked until the ESD event charge is discharged from pad 202 through PNP transistor Q1.
In the embodiment of FIG. 2, the magnitude of NiGBT trigger voltage (VT1) varies inversely with the magnitude of resistance coupled between the gate of NMOS transistor M1 and ground. Thus, when signal output circuitry 200 and low voltage supply rail VDDL of signal output circuitry 200 is unpowered, NMOS switching element is off (or open) so that resistance between the gate of NMOS transistor M1 and ground is equal to RG, which acts to lower VT1 (e.g., to about 80 volts in one exemplary embodiment). This may be advantageously implemented to sufficiently lower the NiGBT trigger voltage (VT1) during circuit fabrication and assembly to ensure that the NiGBT device 280 is triggered during an ESD event and before the unpowered buffer circuit 270 (that the NiGBT device 280 is protecting) is triggered, which is desirable since breakdown voltage of output transistors 210 and 212 may otherwise be close to the trigger voltage VT1 of the NiGBT device 280. It will be understood that the particular lowered value of VT1 may vary in other embodiments (e.g., may be greater than or less than 80 volts) based on the characteristics of a given NiGBT device 280 in combination with a particular selected resistance value of RG that is selected for a given circuit at risk.
However, when signal output circuitry 200 is powered on (e.g., to about 150 volts in one exemplary embodiment), low voltage supply rail VDDL of signal output circuitry 200 is powered on. In this case, NMOS switching element is turned on (or closed) so that the gate of NMOS transistor M1 is shorted (and strongly coupled) to ground, e.g., similar to wiring the gate of M1 to ground. This in turn acts to raise VT1 to a value (e.g., to about 155 volts in one exemplary embodiment) that is greater than the normal operating voltage of the output buffer circuit 270 that the NiGBT device 280 is protecting. Thus, when signal output circuitry 200 (and VDDL) is powered on, NiGBT trigger voltage (VT1) is controlled to be a value that is greater than the normal operating voltage of the output buffer circuit 270 that the NiGBT device 280 is protecting so that NiGBT device 280 does not discharge current from pad 202 under normal operating voltage conditions in the absence of ESD event 290. It will be understood that the particular raised value of VT1 may vary in other embodiments (e.g., may be greater than or less than 155 volts) based on the characteristics of a given NiGBT device 280.
FIG. 3 illustrates a partial cross section of a silicon-on-insulator (SOI) device structure 300 of NiGBT circuit device 280 according to one exemplary embodiment. In this embodiment, NiGBT structure 300 includes a buried oxide (e.g., BOX) layer 306 and top silicon semiconductor layer 309 (e.g., silicon or germanium-based) formed on P-type substrate 304. In this embodiment, a P+ type body region 312 and Nwell 308 (that are separated by a lightly doped (N−) high voltage Nwell drift region 310) are formed in top silicon semiconductor layer 309 above BOX (e.g., silicon dioxide) layer 306 as shown. As further shown, a Pwell 314 is formed in top silicon semiconductor layer 309 adjacent P+ body region 312, and a PDD region 318 is formed in Pwell 314 and P+ body region 312. P+ doped region 320 is formed within Nwell 308 to form an anode of NiGBT device structure 300 that is coupled to signal output signal pad 202 by conductive (e.g., metal) pad 351. N+ doped region 324 and P+ doped region 326 are formed within lightly doped PDD region 318 and Pwell 314 to form a cathode of NiGBT device structure 300 that is coupled to ground via conductive (e.g., metal) pads 353 and 352 as shown. In this configuration, N+ doped region 324 forms a source terminal for NMOS transistor M1, P+ doped region 326 forms a body terminal for NMOS transistor M1, while Nwell drift region 310 and Nwell 308 together form a drain for NMOS transistor M1. Conductive (e.g., metal) gate terminal 354 and gate oxide 355 for NMOS transistor M1 are formed as shown above P+ body region 312 and Nwell drift region 310, with gate terminal 354 being coupled as shown to ground via gate control circuit 295 and parallel gate resistor RG. Also present in FIG. 3 are field oxide regions 307 and deep trench isolation region 316 that is formed in top silicon semiconductor layer 309.
Still referring to FIG. 3, PNP bipolar transistor Q1 and parasitic NPN bipolar transistor Q2 elements of NiGBT device 280 of FIG. 2 are illustrated in relation to the respective components of NiGBT device structure 300 of FIG. 3. Also illustrated are gate-to-drain capacitance (CGD) and gate-to-source capacitance (CGS) of NMOS transistor M1 that were also described in relation to FIG. 2. Noted here is that since the body of NMOS transistor M1 is shorted in metal to its source CGS=gate-to-body capacitance (CGB).As shown in FIG. 3, the channel length (LCH) of NMOS transistor M1 is defined by the distance that gate 354 overlaps P+ body region 312, and gate-to-source capacitance (CGS) of NMOS transistor M1 is determined by the value of LCH, which in turn affects the magnitude of feedthrough voltage ratio. In general, the feedthrough ratio of ESD potentials coupled from the pad onto the gate of M1 is proportional to CGD/(CGD+CGS). Thus, as the value of LCH (and CGS) decreases for fixed CGD, the feedthrough ratio increases and a larger fraction of the pad voltage is coupled to the gate of M1 which causes a significant decrease in the overall trigger voltage (VT1) of the NiGBT device. As values of LCH become increasingly smaller (e.g., 0.9 μm relative to a fixed length of 10 μm), the propensity increases for NiGBT circuit device 280 to exhibit a reduction in the trigger voltage VT1 during an ESD event.
FIG. 4 is a plot of current versus resistance that illustrates how gate resistor RG of gate control circuit 295 may be sized to selectively decrease the trigger voltage VT1 (i.e., by attenuating CGS and modulating the feedthrough ratio) to fit the unpowered voltage characteristics needed or desired for a NiGBT device 280 having a channel length (LCH) of 0.9 μm. To obtain the data for FIG. 4, a 200 μm wide NiGBT circuit device 280 having the gate of its NMOS transistor M1 tied to ground through gate resistor RG was subjected to transmission line pulse (TLP) testing, in which 100 ns long pulses were applied to the NiGBT device 280 to trigger the NiGBT device 280 to discharge the current pulse. As shown in FIG. 4, baseline NiGBT trigger voltage VT1(0) for the case where the gate of NMOS M1 coupled with no RG resistance to ground is raised to about 155 volts. Little lowering in NiGBT trigger voltage VT1(1) is observed for the case where RG is 1 kΩ, which remains close to about 155 volts. However, NiGBT trigger voltage VT1(5) drops to about 125 volts for the case where RG is 5 kΩ , and drops further to about 98 volts for the case where RG is 10 kΩ Finally, NiGBT trigger voltage VT1(20) drops to about 80 volts for the case where RG is 20 kΩ. Thus, in one embodiment a given NiGBT device configuration (e.g., having a given selected channel length LCH) may be empirically tested or otherwise evaluated (e.g., using simulation) to determine a relationship between varying resistance value of RG and corresponding NiGBT trigger voltage VT1, from which the resistance of resistor RG may be selected to meet a desired or target NiGBT trigger voltage for unpowered circuit conditions.
It will be understood that the exemplary embodiments of FIGS. 2, 3 and 4 are exemplary only, and that other configurations of NiGBT device and/or gate control circuit may be employed to provide ESD protection for various types of integrated circuits. It will also be understood that the disclosed circuitry and methods may be implemented to protect at risk circuitry using insulated-gate bipolar transistor (IGBT) device circuitry having a variety of different channel lengths (LCHs), such as using IGBT device circuitry having a LCH that is less than 10 microns, alternatively that is from about 0.5 micron to less than 10 microns, alternatively that is from about 0.5 micron to about 9 microns, alternatively that is from about 0.5 micron to about 8 microns, alternatively that is from about 0.5 micron to about 7 microns, alternatively that is from about 0.5 micron to about 6 microns, alternatively that is from about 0.5 micron to about 5 microns, alternatively that is from about 0.5 micron to about 4 microns, alternatively that is from about 0.5 micron to about 4 microns, alternatively that is from about 0.5 micron to about 3 microns, alternatively that is from about 0.5 micron to about 2 microns, alternatively that is from about 0.5 micron to about 1 micron, and alternatively that is about 0.9 micron, although use of IGBT device circuitry having a LCH that is less than about 0.5 microns or greater than or equal to about 10 microns is also possible.
It will be understood that a given IGBT device configuration having a given selected channel length LCH may be empirically tested or otherwise evaluated (e.g., using simulation) in one embodiment according to the methodology illustrated in FIG. 4 to determine a relationship between varying resistance value of RG and corresponding IGBT trigger voltage VT1 for that particular LCH and IGBT device configuration, from which the resistance of resistor RG may be selected to meet a desired (or target) IGBT trigger voltage for unpowered circuit conditions. It will also be understood that the particular configuration of NMOSFET transistor elements of the circuitry embodiments described and illustrated herein are exemplary only, and may be replaced by equivalent complementary metal-oxide semiconductor (CMOS) circuitry in which PMOSFET and NMOSFET transistor switching elements are juxtaposed, as will be appreciated by one of ordinary skill in the art with the benefit of this disclosure.
Further, while the invention may be adaptable to various modifications and alternative forms, specific embodiments have been shown by way of example and described herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. Moreover, the different aspects of the disclosed circuitry and methods may be utilized in various combinations and/or independently. Thus the invention is not limited to only those combinations shown herein, but rather may include other combinations.
Patent Application
20170194788
