Patent Application
20230316996
The present disclosure relates to flat-panel display architectures having reduced power use.
Flat-panel displays are widely used in conjunction with computing devices, in portable electronic devices, and for entertainment devices such as televisions. Such displays typically employ an array of pixels distributed over a display substrate to display images, graphics, or text. In a color display, each pixel includes light emitters that emit light of different colors, such as red, green, and blue. For example, liquid crystal displays (LCDs) employ liquid crystals to block or transmit light from a backlight behind the liquid crystals and organic light-emitting diode (OLED) displays rely on passing current through a layer of organic material that glows in response to the current. Displays using inorganic light-emitting diodes (LEDs) as pixel elements are also in widespread use for outdoor signage and have been demonstrated in a 55-inch television.
Displays are typically controlled with either a passive-matrix (PM) control scheme employing electronic control circuitry external to the pixel array or an active-matrix (AM) control scheme employing electronic control and storage circuitry in each pixel on the display substrate associated with each light-emitting element. Both OLED displays and LCDs using passive-matrix control and active-matrix control are available. An example of such an AM OLED display device is disclosed in U.S. Pat. No. 5,550,066.
Mobile electronic devices operate on battery power and frequently include a display. There is a need, therefore, to reduce the power used by a display to increase the amount of time the electronic device can operate before losing sufficient operating power and requiring a battery recharge.
The present disclosure includes, among various embodiments, a flat-panel display with reduced power use. Such displays can be more efficient, can reduce operational costs, and can be particularly useful for mobile electronic devices that operate on battery power.
According to embodiments of the present disclosure, a dynamic-voltage-control pixel comprises a pixel memory, an input circuit operable at a refresh voltage to receive pixel data and store the received pixel data in the pixel memory, a light emitter, and an output circuit operable at a drive voltage to read the stored pixel data from the pixel memory and control the light emitter to output light according to the read stored pixel data. The drive voltage can be less than the refresh voltage.
In some embodiments, the pixel memory has a refresh leakage current at the refresh voltage and a drive leakage current at the drive voltage, and the refresh leakage current is greater than the drive leakage current. The pixel memory can be a static memory.
In some embodiments, a dynamic-voltage-control pixel comprises common-voltage wire connected to the input circuit, the pixel memory, and the output circuit.
In some embodiments, any one or more of the input circuit, the pixel memory, and the output circuit are electrically connected to a refresh-voltage wire and a drive-voltage wire separate from the refresh-voltage wire and wherein the any one or more of the input circuit, the pixel memory, and the output circuit comprises a voltage-selection circuit for selecting the drive-voltage wire or the refresh-voltage wire. In some embodiments, the input circuit can be electrically connected to only the refresh-voltage wire or the output circuit can be electrically connected to only the drive-voltage wire, or both. The pixel memory can be electrically connected to both the refresh-voltage wire and the drive-voltage wire and can comprise a voltage-selection circuit for selecting the drive-voltage wire or the refresh-voltage wire (e.g., selects the voltage provided on the drive-voltage wire or the refresh-voltage wire).
According to some embodiments of the present disclosure, a dynamic-voltage-control display comprises a pixel array of dynamic-voltage-control pixels and a display controller operable to control the dynamic-voltage-control pixels. The display controller can be operable to provide the drive voltage to the dynamic-voltage-control pixels in a drive mode and provide the refresh voltage in a refresh mode. The dynamic-voltage-control pixels can be operable to (i) receive respective pixel data and store the respective pixel data in the pixel memory in the refresh mode and (ii) read the respective stored pixel data from the pixel memory and then control the light emitter to output light according to the respective pixel data in the drive mode.
In some embodiments, the dynamic-voltage-control pixels can be connected in common to a common-voltage wire controlled by the display controller to provide the refresh voltage in a refresh mode on the common-voltage wire and to provide the drive voltage in a drive mode to the dynamic-voltage-control pixels on the common-voltage wire.
In some embodiments, the dynamic-voltage-control pixels in the array are arranged in rows and columns and the dynamic-voltage-control pixels in each of the rows are connected in common to a common row voltage wire for the row that is controlled by the display controller. The display controller can be operable to provide the refresh voltage to a refresh row of the rows and the drive voltage to drive rows of the rows that are each different from the refresh row. The display controller can be operable to provide pixel data to each of the dynamic-voltage-control pixels at a refresh rate and the refresh voltage can be directly dependent on the refresh rate. The display controller can be operable to provide pixel data to each of the dynamic-voltage-control pixels at a refresh rate and the output circuit of the dynamic-voltage-control pixel can be operable to control the light emitter of the dynamic-voltage-control pixel to emit light at an output rate greater than the refresh rate. The display controller can be operable to provide pixel data to the dynamic-voltage-control pixels at a data rate that can be directly dependent on the refresh rate.
In some embodiments, at least some of the dynamic-voltage-control pixels are connected to a refresh voltage wire controlled by the display controller and to a drive voltage wire controlled by the display controller, and the display controller is operable to (i) provide the refresh voltage to the refresh voltage wire and pixel data to the at least some of the dynamic-voltage-control pixels that are in a row of pixels at the refresh voltage in a refresh mode and (ii) provide a zero voltage to the refresh voltage wire to the row of pixels in a drive mode.
According to embodiments of the present disclosure, a method of controlling a dynamic-voltage-control display comprises providing the refresh voltage to the at least some of the dynamic-voltage-control pixels on the refresh voltage wire, refreshing the pixel memory of the at least some of the dynamic-voltage-control pixels with the pixel data, providing the drive voltage to the at least some of the dynamic-voltage-control pixels on the drive voltage wire, and providing a zero voltage to the at least some of the dynamic-voltage-control pixels on the refresh voltage wire.
According to embodiments of the present disclosure, a method of controlling a dynamic-voltage-control pixel comprises providing the refresh voltage to the dynamic-voltage-control pixel, refreshing the pixel memory with the pixel data, providing the drive voltage to the dynamic-voltage-control pixel, and reading the pixel data from the pixel memory and controlling the light emitter to output light corresponding to the pixel data. Some embodiments comprise providing the refresh voltage to a refresh row of the dynamic-voltage-control pixels and providing pixel data to the refresh row of the pixels and providing the drive voltage to drive rows of the dynamic-voltage-control pixels other than the refresh row of dynamic-voltage-control pixels and driving the light emitters of the dynamic-voltage-control pixels in the drive rows to emit light. Some embodiments comprise successively selecting different refresh rows of the pixels. Some embodiments comprise providing pixel data to the refresh row of dynamic-voltage-control pixels at a refresh rate and driving the dynamic-voltage-control pixels in the drive rows of dynamic-voltage-control pixels at a drive rate, and the drive rate is greater than the refresh rate.
According to embodiments of the present disclosure, a dynamic-voltage-control circuit comprises a circuit memory, an input circuit operable at a refresh voltage to receive circuit data and store the circuit data in the circuit memory, a functional circuit, and a functional drive circuit operable at a drive voltage to read the circuit data from the circuit memory and then control the functional circuit to operate according to the circuit data. The drive voltage can be less than the refresh voltage.
According to some embodiments of the present disclosure, the pixels in the array of pixels comprise inorganic light-emitting diodes, for example micro-light-emitting diodes and each of the one or more inorganic micro-light-emitting-diodes has a length and a width each no greater than 200 microns.
Embodiments of the present disclosure provide active-matrix display and pixel control methods and architectures that reduce display power use.
The foregoing and other objects, aspects, features, and advantages of the present disclosure will become more apparent and better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:
Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings, in which like reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The figures are not drawn to scale since the variation in size of various elements in the Figures is too great to permit depiction to scale.
The row and column signal driving circuits in a matrix-addressed flat-panel pixel array disposed on a substrate must electrically drive row and column signals at the desired frequency and distance over the substrate and maintain row and column signal integrity to every row and column of pixels in the array. For large arrays driven at a fast frame rate on a large substrate, the row and column signals can degrade because of row and column wire resistance, parasitic capacitance and inductance, and transmission line impedance discontinuities. Embodiments of the present disclosure provide, inter alia, dynamic-voltage-control pixel array methods and architectures that enable improved control and signal distribution for flat-panel active-matrix arrays (e.g., flat-panel arrays with a relatively large substrate and many pixels). The dynamic-voltage-control pixels can comprise inorganic light-emitting diodes and the dynamic-voltage-control pixel arrays can comprise analog or digital pixels in displays. In some embodiments, the dynamic-voltage-control pixels can comprise inorganic micro-LEDs and the dynamic-voltage-control pixel array can be a micro-LED display.
According to embodiments of the present disclosure and as illustrated in
Pixel memory 22 can have a refresh leakage current at the refresh voltage 42 and a drive leakage current at the drive voltage 44. The refresh leakage current can be greater than the drive leakage current. According to embodiments of the present disclosure, pixel memory 22 can be a static memory (e.g., a random access memory or a register).
In some embodiments, input circuit 24, pixel memory 22, and output circuit 26 are all connected to and operate on a common-voltage wire 40. In embodiments of the present disclosure, an electrically conductive wire provides an electrical connection, for example between two electronic circuit elements, devices, or components. Row controller 50R and column controller 50C can also operate at or provide signals at a desired voltage (e.g., refresh voltage 42 or drive voltage 44) on corresponding row wires 52R and column wires 52C. (For clarity in the figures, element 40 refers to both the common voltage 40 and to the common-voltage wire 40 or connection providing common voltage 40. Element 42 refers to both the refresh voltage 42 and to the refresh-voltage wire 42 or connection providing refresh voltage 42. Element 44 refers to both the drive voltage 44 and to the drive-voltage wire 44 or connection providing drive voltage 44.) According to embodiments of the present disclosure, operating pixel memory 22 (and dynamic-voltage-control pixel 20) at drive voltage 44 reduces power use because less current is lost through leakage, e.g., through transistor gate dielectrics. In particular, leakage through a transistor-based memory can be a significant power drain particularly for large memory arrays (e.g., as found in large, high-resolution displays) constructed with small, high-resolution transistors comprising thin dielectric materials through which current can more readily leak. This leakage effect can be substantial for small transistors, particularly for those with resolutions (nodes) less than 50 nm, less than 20 nm, less than 10 nm, or less than 5 nm. Moreover, the power loss can increase at a rate greater than a linear rate related to the resolution. Thus, operating the memory at a reduced voltage when reading the memory contents out to display the contents through one or more light emitters 30 can reduce power loss. However, communicating pixel data over a large substrate at a relatively low voltage reduces the signal-to-noise ratio of the communicated pixel data. Display circuits can be electrically noisy, have a limited conductivity, width, or depth due to limited area on a display substrate, operate at a relatively high frequency, or a combination of these, making signal-to-noise ratios on row wires 52R and column wires 52C an important concern. Hence, a higher voltage is preferred to transmit data into a pixel (e.g., row-select signals on row wires 52R and column-data signals on column wires 52C) but a lower voltage is preferred to operate dynamic-voltage-control pixel 20, pixel memory 22, or output circuit 26. In some embodiments, an output (display) rate for pixel data in pixel memory 22 is greater than an input (refresh) rate for pixel data, so that the amount of time spent updating pixel data at refresh voltage 42 is smaller than the amount of time spent displaying data at drive voltage 44. Thus, according to embodiments of the present disclosure, a pixel can reduce power loss and improve function by operating at a relatively higher refresh voltage 42 with an improved signal-to-noise ratio to receive pixel data and by operating at a relatively lower drive voltage 44 with reduced current leakage to display pixel data. The amount of time dynamic-voltage-control pixel 20 spends operating at refresh voltage 42 can be less than the time spent operating at drive voltage 44.
In operation, display controller 50 provides information and control signals to row controller 50R (e.g., timing signals, row-select signals, or common voltages 40 on a common-voltage wire 40) and pixel data and control signals to column controller 50C (e.g., column-data signals). Dynamic-voltage-control pixels 20 receive the row and column signals from row wires 52R and column wires 52C and display received information with one or more light emitters 30 (e.g., light-emitting diodes or LEDs such as inorganic LEDs). Display controller 50 (e.g., comprising row controller 50R or column controller 50C, or both) controls dynamic-voltage-control pixels 20 in a display, for example using a voltage selector 46 or multiplexer disposed in the row or column controller 50R, 50C responsive to a refresh or drive mode-select signal 48 as shown in the
Thus, according to embodiments of the present disclosure, a dynamic-voltage-control display 90 comprises dynamic-voltage-control pixels 20 and display controller 50 operable to control the dynamic-voltage-control pixels 20. Display controller 50 is operable to provide drive voltage 44 to dynamic-voltage-control pixels 20 in a drive mode and provide refresh voltage 42 in a refresh mode and is operable to provide control and data signals (e.g., row-select signals on row wires 52R and column-data signals on column wires 52C) at refresh voltage 42. Dynamic-voltage-control pixels 20 are operable to (i) receive pixel data and store the received pixel data in pixel memory 22 in the refresh mode and (ii) read the stored pixel data from pixel memory 22 and control light emitter 30 to output light according to the read stored pixel data in the drive mode. In some embodiments, the refresh mode (and use of refresh voltage 42) is less frequent than the drive mode (and use of drive voltage 44) for pixel data output. In some embodiments, the refresh mode is on-demand and updated pixel data is supplied to dynamic-voltage-control pixel 20 only when new pixel data is available.
As shown in the timing diagram of
In operation, mode-select signal 48 is set to refresh mode (e.g., by row controller 50R or column controller 50C), signals are transmitted to input circuit 24 at refresh voltage 42 and at least input circuit 24 operates at refresh voltage 42 to receive the transmitted signals (e.g., row-select, timing, control, or column-data signals). Pixel memory 22 can optionally select and operate at refresh voltage 42 in response to input circuit 24. Output circuit 26 can, but does not necessarily select and operate at refresh voltage 42. In some embodiments, output circuit 26 operates only at drive voltage 44. Once pixel data has been received by pixel memory 22, all of pixel memory 22, input circuit 24, and output circuit 26 can select and operate at drive voltage 44 (e.g., in response to mode-select signal 48 (e.g., provided by display controller 50) to output pixel data to light-emitter drive circuit 32 and light emitter 30. Thus, in some embodiments of the present disclosure, an input circuit 24 comprises a refresh-voltage wire 42 and a drive-voltage wire 44 separate refresh-voltage wire 42 and input circuit 24 comprises a voltage-selection circuit for selecting the drive-voltage wire 44 or the refresh-voltage wire 42.
In some embodiments, refresh voltage 42 can be set to zero volts in drive mode and input circuit 24 can be turned off, further saving power in dynamic-voltage-control pixel 20. In some such embodiments, voltage selector 46 of input circuit 24 selects between drive voltage 44 and zero volts responsive to mode-select signal 48. Thus, in some embodiments, dynamic-voltage-control pixels 20 are connected to a refresh-voltage wire 42 controlled by display controller 50 and a drive-voltage wire 44 controlled by display controller 50. Display controller 50 can be operable to (i) provide refresh voltage 42 to refresh-voltage wire 42 and pixel data to the dynamic-voltage control pixels 20 in a row of dynamic-voltage control pixels 20 at the refresh voltage 42 in a refresh mode and (ii) provide a zero voltage to refresh-voltage wire 42 to the row of dynamic-voltage control pixels 20 in a drive mode.
As illustrated in
Flow diagram 5 illustrates an overall process for dynamic-voltage-control display 90. Dynamic-voltage-control display 90 and pixel data are provided in step 100. In step 110, dynamic-voltage-control pixels 20 are provided with power at refresh voltage 42 on the refresh-voltage wire 42 and pixel data is loaded into pixel memory 22 in step 120. Once the pixel data is loaded, dynamic-voltage-control pixels 20 are provided with power at drive voltage 44 on the drive-voltage wire 44 in step 130 and pixel data is provided to light emitter 30 in step 140. The process can then be repeated when new pixel data is available.
Dynamic-voltage-control display 90 can comprise dynamic-voltage-control pixels 20 disposed in rows and columns over display substrate 10, as shown in
As shown in
As shown in
Thus, according to embodiments of the present disclosure, display controller 50 is operable to provide refresh voltage 42 to a refresh row and drive voltage 44 to drive rows. In some embodiments, drive rows are rows of pixel array 12 that are not a refresh row.
Signal-to-noise ratio can be dependent on both signal voltage and signal frequency. Thus, a selected refresh voltage 42 can depend on the frequency of a refresh signal (e.g., row-select or column-data signals). In some embodiments, display controller 50 is operable to provide pixel data to each dynamic-voltage-control pixel 20 at a refresh rate (frequency) and refresh voltage 42 is directly dependent on the refresh rate (frequency). If the refresh rate decreases, refresh voltage 42 can also decrease. The refresh rate can be a data rate, e.g., a rate at which pixel data is provide to dynamic-voltage-control pixel 20. The data rate then is likewise directly dependent on the refresh rate. In some embodiments, output circuit 26 is operable to control light emitter 30 to emit light at an output rate greater than the refresh rate. Such a greater output rate can reduce flicker in dynamic-voltage-control display 90.
Embodiments of the present disclosure illustrated in
In embodiments of the present disclosure, drive voltage 44 can be no greater than 2 volts, no greater than 1.5 volts, no greater than 1.2 volts, no greater than 1.1 volts, no greater than 1.0 volts, no greater than 0.9 volts, no greater than 0.8 volts, or no greater than 0.7 volts so that dynamic-voltage-control display 90 operates at such voltages during the drive mode. Such relatively low drive voltages 44 compared to refresh voltage 42 (e.g., no less than 2 volts, no less than 2.3 volts, or no less than 2.5 volts) can greatly reduce leakage current, especially at photolithographic process resolutions (nodes) no greater than 100 nm, no greater than 60 nm, no greater than 50 nm, no greater than 40 nm, no greater than 30 nm, no greater than 20 nm, no greater than 10 nm, or no greater than 5 nm. Leakage current due to thinner gate dielectrics can increase at a greater-than-linear rate as process resolution decreases and can be reduced at a greater-than-linear rate as operating voltage decreases, thus improving power efficiency in dynamic-voltage-control display 90.
Dynamic-voltage-control pixel 20 can be or comprise a bare unpackaged integrated circuit disposed on display substrate 10, for example by micro-transfer printing, having an integrated circuit substrate separate, individual, and independent of and non-native to display substrate 10. The bare, unpackaged integrated circuit can be a CMOS silicon integrated circuit and can have a length or width no greater than 200 μm (e.g., no greater than 100 μm, no greater than 50 μm, or no greater than 20 μm, or no greater than 10 μm) and a thickness no greater than 50 μm (e.g., no greater than 20 μm, no greater than 10 μm or no greater than 5 μm). In some embodiments, display substrate 10 can be a semiconductor substrate (e.g., a silicon substrate) and dynamic-voltage-control pixel 20 can be native to display substrate 10. In some embodiments, dynamic-voltage-control pixel 20 can be or comprise a thin-film circuit disposed on and native to display substrate 10. In some embodiments, dynamic-voltage-control pixel 20 can be disposed with light emitter 30 and light-emitter drive circuit 32 on a pixel substrate to form a pixel module separate from display substrate 10.
Row or column controllers 50R, 50C can be integrated circuits providing control, input, and output signals, for example onto row or column wires 52R, 52C. Row and column wires 52R, 52C can comprise any patterned electrically conductive material, such as a metal, metal alloy, transparent conductive metal oxide, or electrically conductive polymer disposed over display substrate 10 and designed to transmit electrical signals such as row-select or column-data signals.
Row and column wires 52R, 52C that transmit the electrical signals have a resistance, parasitic capacitance, inductance, and reactance, and can have transmission line impedance discontinuities (e.g., IR drop and impedance of the signal wires) that limit the rate at which data can be transmitted on the signal wires with an acceptable signal-to-noise ratio and hence the refresh rate and size of pixel array 12 of dynamic-voltage-control pixels 20 on display substrate 10. More powerful drive circuitry in row or column controllers 50R, 50C or dynamic-voltage-control pixels 20 and careful transmission line design can mitigate, but not eliminate, this limitation. According to embodiments of the present disclosure, the use of refresh voltage 42 greater than display voltage 44 in dynamic-voltage-control pixels 20 refresh (input or update) mode or drive (output or display) mode, respectively, provides improved signal-to-noise ratio for pixel data communication and also reduces power use in dynamic-voltage-control display 90.
In some embodiments, dynamic-voltage-control pixels 20 comprise more than one light emitter 30 or light-emitter drive circuit 32. For example, dynamic-voltage-control pixels 20 can comprise three light emitters 30, for example one each for a red, green, and blue light emitter 30, together with sufficient pixel memory 22 to store corresponding pixel data.
Display substrate 10 can be any useful substrate on which pixel array 12 of dynamic-voltage-control pixels 20, row wires 52R, and column wires 52C can be suitably disposed. Display substrate 10 can be flexible or rigid and can be substantially flat. Generally, display substrate 10 has two opposing smooth sides suitable for material deposition, photolithographic processing, or micro-transfer printing of light emitters 30. Display substrate 10 can have a size of a conventional display, for example a rectangle with a diagonal of a few centimeters to one or more meters. Display substrate 10 can include polymer, plastic, resin, fiberglass, polyimide, PEN, PET, metal, metal foil, glass, a semiconductor, ceramic, quartz, sapphire, or other substrates found in the display or integrated circuit industries and can have a transparency greater than or equal to 50%, 80%, 90%, or 95% for visible light. In some embodiments of the present disclosure, light emitters 30 emit light through display substrate 10. In some embodiments, light emitters 30 emit light in a direction opposite display substrate 10. Display substrate 10 can have a thickness from 5 μm to 20 mm (e.g., 5 to 10 μm, 10 to 50 μm, 50 to 100 μm, 100 to 200 μm, 200 to 500 μm, 500 μm to 0.5 mm, 0.5 to 1 mm, 1 mm to 5 mm, 5 mm to 10 mm, or 10 mm to 20 mm). According to some embodiments of the present disclosure, display substrate 10 can include layers formed on an underlying structure or substrate, for example a rigid or flexible glass or plastic substrate.
Column wires 52C and row wires 52R can be conductive wires (e.g., photolithographically defined electrical conductors such as metal lines) disposed on display substrate 10 that conduct electrical current from column and row controllers 50C, 50R, respectively, to dynamic-voltage-control pixels 20. In matrix-addressed flat-panel pixel array 12, column wires 52C can conduct column signals such as column data signals and row wires 52R can conduct row signals such as timing or control signals, for example row-select signals. Column and row designations are arbitrary and can be interchanged without affecting the embodiments described in the present disclosure. Column controller 50C can be, for example, an integrated circuit that provides control, timing (e.g., clocks) or data signals (e.g., column-data signals) through column wires 52C to pixel columns of dynamic-voltage-control pixels 20 to enable dynamic-voltage-control pixels 20 to control light emitters 30 in dynamic-voltage-control display 90. Each column wire 52C can be electrically separate and optionally independently controlled from every other column wire 52C by column controller 50C. Column controller 50C can comprise a single integrated circuit or can comprise multiple integrated circuits, e.g., electrically connected integrated circuits. The integrated circuit(s) can be micro-transfer printed as bare unpackaged dies and can comprise broken (e.g., fractured) or separated tether(s).
Row controller 50R can be, for example, an integrated circuit that provides control signals (e.g., row-select signals) and/or timing signals (e.g., clocks or timing signals such as pulse-width modulation (PWM) signals) through row wires 52R to pixel rows of dynamic-voltage-control pixels 20 to cause dynamic-voltage-control pixels 20 to control light emitters 30 in dynamic-voltage-control display 90. Each row wire 52R can be electrically separate and optionally independently controlled from every other row wire 52R by row controller 50R. Row controller 50R can comprise a single integrated circuit or can comprise multiple integrated circuits, e.g., electrically connected integrated circuits. The integrated circuit(s) can be micro-transfer printed as bare unpackaged dies and can comprise broken (e.g., fractured) or separated tether(s).
Pixel array 12 of dynamic-voltage-control pixels 20 can be a completely regular pixel array 12 (e.g., as shown in
Dynamic-voltage-control pixels 20 can be active- or passive-matrix dynamic-voltage-control pixels 20, can be analog or digital, and can comprise one or more light emitters 30. Dynamic-voltage-control pixels 20 can comprise micro-light-emitting diodes, e.g., inorganic light-emitting diodes such as horizontal inorganic light-emitting diodes or vertical inorganic light-emitting diodes (not shown in the Figures). Inorganic light-emitting diodes can have a small area, for example having a length and a width each no greater than 10 μm, no greater than 20 μm, no greater than 50 μm, no greater than 100 μm, or no greater than 200 μm.
In a method according to some embodiments of the present disclosure, integrated circuits (e.g., comprising dynamic-voltage-control pixels 20) are disposed on display substrate 10 by micro transfer printing. In some methods, integrated circuits (or portions thereof) or light emitters 30 (e.g., micro-LEDs) are disposed on a pixel substrate to form a heterogeneous dynamic-voltage-control pixel 20 and dynamic-voltage-control pixel 20 is disposed on display substrate 10 using compound micro-assembly structures and methods, for example as described in U.S. patent application Ser. No. 14/822,868 filed Aug. 10, 2015, entitled Compound Micro-Assembly Strategies and Devices. In some methods of the present disclosure, dynamic-voltage-control pixels 20 are disposed on display substrate 10 using pick-and-place methods found in the printed-circuit board industry, for example using vacuum grippers. Dynamic-voltage-control pixels 20 can be interconnected on display substrate 10 using photolithographic methods and materials or printed circuit board methods and materials.
In certain embodiments, display substrate 10 includes material, for example glass or plastic, different from a material in an integrated-circuit substrate, for example a semiconductor material such as silicon or GaN. Light emitters 30 can be formed separately on separate semiconductor substrates, assembled onto pixel substrates to form dynamic-voltage-control pixels 20 and then the assembled units are located on the surface of display substrate 10. This arrangement has the advantage that the integrated circuits or dynamic-voltage-control pixels 20 can be separately tested on pixel substrate and the pixel modules accepted, repaired, or discarded before dynamic-voltage-control pixels 20 are located on display substrate 10, thus improving yields and reducing costs.
In some embodiments, red, green, and blue light emitters 30 (e.g., micro-LEDs) are micro transfer printed to pixel substrates or display substrate 10 in one or more transfers and can comprise broken (e.g., fractured) or separated LED tethers as a consequence of micro-transfer printing. For a discussion of micro-transfer printing techniques that can be used or adapted for use in methods disclosed herein, see U.S. Pat. Nos. 8,722,458, 7,622,367 and 8,506,867, each of which is hereby incorporated by reference in its entirety. The transferred light emitters 30 are then electrically connected to dynamic-voltage-control pixels 20, for example with conductive wires and optionally including connection pads and other electrical connection structures, to enable a column controller 50C or row controller 50R to electrically interact with dynamic-voltage-control pixels 20 and therefore enable light-emitters 30 to emit light.
In some embodiments of the present disclosure, pixel array 12 of dynamic-voltage-control pixels 20 (e.g., as in
By employing a multi-step transfer or assembly process, increased yields are achieved and thus reduced costs for pixel arrays 12 of the present disclosure. Additional details useful in understanding and performing aspects of the present disclosure are described in U.S. patent application Ser. No. 14/743,981, filed Jun. 18, 2015, entitled Micro Assembled Micro LED Displays and Lighting Elements, the disclosure of which is hereby incorporated by reference herein in its entirety.
As is understood by those skilled in the art, the terms “over”, “under”, “above”, “below”, “beneath”, and “on” are relative terms and can be interchanged in reference to different orientations of the layers, elements, and substrates included in the present disclosure. For example, a first layer on a second layer, in some embodiments means a first layer directly on and in contact with a second layer. In other embodiments, a first layer on a second layer can include another layer there between.
As is also understood by those skilled in the art, the terms “column” and “row”, “horizontal” and “vertical”, and “x” and “y”, “top” and “bottom”, and “left” and “right” are arbitrary designations that can be interchanged (unless otherwise clear from context).
Throughout the description, where apparatus and systems are described as having, including, or comprising specific components, or where processes and methods are described as having, including, or comprising specific steps, it is contemplated that, additionally, there are apparatus, and systems of the disclosed technology that consist essentially of, or consist of, the recited components, and that there are processes and methods according to the disclosed technology that consist essentially of, or consist of, the recited processing steps.
It should be understood that the order of steps or order for performing certain action is immaterial so long as operability is maintained. Moreover, two or more steps or actions in some circumstances can be conducted simultaneously. The disclosure has been described in detail with particular express reference to certain embodiments thereof, but it will be understood that variations and modifications can be effected within the spirit and scope of the following claims.
