Patent Application
20060273842
Embodiments of this invention relate to integrated circuits, and particularly to sense amplifier or other CMOS circuits with improved margins at lower voltages.
As integrated circuit technology progresses, the feature sizes of the circuitry and the voltages used to stimulate them continue to decline. As voltages decrease, it becomes more difficult to sense particular voltages. Consider for example the sense amplifier (sense amp) 30 of
As operating voltages are lowered, it can become more difficult for the sense amp 30 to properly function. In particular, the inventors have noticed that the N-channel (NCH) transistors in the sense amp 30 may not turn on (or may not turn on enough) when desired because the sensed voltages are relatively small compared to the threshold voltage of the NCH transistors (NVt). It is desired to remedy this problem, and more generally to provide a solution to reduced sensing margins caused by lower operating voltages in other non-sense-amp contexts as well, such as in general Complementary Metal Oxide Semiconductor (CMOS) circuitry.
In one embodiment of the invention, the p- well back bias for the NCH transistors in a DRAM sense amplifier circuit are dynamically adjusted. Preferably, during sensing, the p- well back bias for the NCH transistors of the sense amps is increased to in effect lower the threshold voltages for the NCH transistors so that they are more easily activated during sensing. The back bias voltage is preferably increased from ground (its normal value) to the threshold voltage of a NCH transistor (NVt), a value low enough to prevent the circuit from latch-up. Moreover, this voltage is preferably arrived at using a Vt detector/bias circuitry which receives the p- well bias voltage as feedback. While benefiting the disclosed sense amp circuit, the dynamic bias provided to the p- well of the NCH transistors can also benefit NCH transistors in other CMOS circuitry as well. Moreover, similar modifications to dynamically bias the n- wells of PCH transistors in CMOS circuits are also provided to increase the sensing margins of PCH transistors as well.
Embodiments of the inventive aspects of this disclosure will be best understood with reference to the following detailed description, when read in conjunction with the accompanying drawings, in which:
Referring again briefly to
Referring now to
As just noted, the preferred embodiment of the disclosed technique is dynamic. This dynamic nature comprises two aspects. First, adjusting the p- wells 25 of the sense amps 30 occurs only during certain times in the operation of the chip, i.e., while sensing. During other times (e.g., when the cells are being precharged), the p- wells 25 are biased to normal values, i.e., ground. Selective activation of the p- well bias is preferred to reduce stand-by current during those times when well bias is not needed (i.e., non-sensing periods). However, if preferred and if standby current is not an issue, the p- wells 25 can be biased at all times and never grounded as in traditional p- wells. The second aspect comprises the voltage to which the p- wells are biased during sensing. As will be seen, the bias provided to the p- wells 25 is not a set voltage, but rather comprises a voltage that is detected and fed back so that it can be adjusted in real time. As will be seen, the use of feedback helps to ensure that the bias voltage provided to the p- wells 25 is not too high, and otherwise ensures a bias voltage appropriate for the processing, temperature, and voltage environment in question, which can be variable.
Before explaining the operation of the p- well bias circuitry 50, note that the stages in bias circuit 70 (four of which are shown) are connected in parallel. Because of this, one skilled in the art will recognize that these stages could be combined together into one large stage. However, because the bank of sense amps 80 are distributed along the edge of an array of cells, the biasing stages in bias circuit 70 are preferably similarly distributed to ensure even power distribution to the various sense amps 30. Preferably one such stage in bias circuit 70 will provide the p- well 25 bias voltage to some fixed number of sense amps (e.g., 16, 32, 64, 128, etc.).
The initial conditions of p- well bias circuit 50 (i.e., prior to sensing) are that the output of logic 90 is high; Node A is brought low by virtue of inverter 92 (note that pass gate 102, while not strictly necessary, is useful to preventing latch up); Node C is high (i.e., the opposite of Node A via inverter 94); Node B is low; and Node D is low (as Node C has turned on NCH transistors 106). As Node D is coupled to the contacts 25′ for the p- wells 25, the p- well bias is ground during periods when no sensing is taking place.
When sensing is to begin, and a non-ground p- well bias is to be provided to the p- wells 25, Node C is taken low by manipulating the control signals to output a low signal from logic 90. By bringing Node C low, NCH transistors 106 are off, and the p- well contacts 25′ are decoupled from ground. Bringing Node C low in turn causes Node A to go high. With the bias circuit 70 now powered by Node A being high, the output of the bias circuit, Node D, will tend to increase to Node A's voltage, a point which is especially true when it is remembered that Node B was initially low, such that PCH transistors 104 were on to encourage the coupling of Nodes A and D.
As Node D increases, eventually NCH transistor 96 will turn on, which pulls the input of inverter 100 low, and its output (Node B) high. When Node B is brought high, Nodes A and D are now decoupled, preventing Node D from further increasing. Thus, the circuit reaches a steady state via the described feedback mechanism such that Node D is encouraged to remain at the switching point between NCH transistor 96 being on and off, i.e., at NVt. Because Node D is coupled to the p- well contacts 25′, the p- wells 25 are thus biased to NVt. As noted earlier, this increased back bias to the p- wells effectively reduces the threshold voltages of the NCH transistors in the sense amp, so that they are easier to turn on.
By biasing the p- wells 25 to NVt, the p- wells are intelligently biased not to a fixed value, but to a value which like other aspects of the integrated circuit will vary with process, voltages, and temperatures. Thus, the disclosed approach, with its reliance on feedback, is preferable to the provision of otherwise set voltages to the p- wells 25. This is important, because the circuit 50 may not behave properly if the p- wells 25 are not biased to the proper level, and particularly will not behave properly if biased too high. For example, note that an NCH transistor (such as those used in sense amp 30) will often have an n+ source or drain region coupled to a ground signal. If the p- well 25 bias is too high, the diode formed by the p- well 25 and the n+ source or drain region may become forward biased, draining current and increasing the risk of latch-up. By ensuring that the p- wells 25 are kept no higher than NVt, and controlling the same to be less than a diode Vt, proper circuit performance can be assured, even given process, voltage and temperature variations. However, a set voltage, not tailored by feedback, could also be used to bias the p- wells 25 in other useful (although non-preferred) embodiments.
Of course, use of the disclosed Vt detection circuit 60, biasing circuit 70, and the manners in which they are interconnected to provide controlled feedback of the p- well bias voltage, are merely exemplary. Other circuits and circuit arrangements are possible to achieve the same results. For example, circuit 110, as well as providing a ground to the p- wells 25 when the sense amps 30 are not sensing, could also include a clamp circuit to prevent the p- well bias from growing too high in value.
Further unexpectedly beneficial results flow from the reduction of the NCH threshold voltages in a DRAM sense amp 30 that are worthy of note. The sense amp 30 preferably is able to discern small differences in the voltages appearing on Digit and Digit*. (See
To this point, the solution to the problem of NCH operation at low operating voltages has centered on the sense amps of DRAM devices. Such circuits are good candidates to benefit from the disclosed technique, because they are particularly voltage and timing sensitive. However, other operative CMOS circuits can also benefit from this technique. For example, as shown in
Moreover, the disclosed techniques are adaptable to adjust the bias of n- wells 20, and hence to adjustment the threshold voltages of PCH transistors (PVt). This is illustrated schematically in
In short, it should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent.
