Fawcett et al, "Reconfigurable Processing with Field Programmable Gate Arrays", IEEE Proceedings of the International Conference on Application Specific Systems, Architectures and Processors, pp. 293-302, Aug. 1996. |
Rabaey, "Reconfigurable Processing: The Solution to Low-Power Programmable DSP", IEEE 1997 International Conference on Acoustics, Speech, and Signal Processing, pp. 275-278, Apr. 1997. |
Rabaey et al, "Heterogeneous Reconfigurable Systems", IEEE 1997 Workshop on Signal Processing Systems, pp. 24-34, Nov. 1997. |
The FIPSOC Page--FIPSOC Field Programmable System On Chip, ESPRIT Project Nr 21625, downloaded from http://www.sidsa.es/fipsoc.htm on Jan. 9, 1998, 5 sheets. |
Application Brief "An Alternative Capacity Metric for LUT-Based FPGAs," published Feb. 1, 1997 (Version 1.0), pp. 1-5. |
Alfke, P., "FPGA Configured Guidelines," Jun. 1, 1996, (Version 1.0), pp. 14-25 to 14-32. |
Alfke, P., "Configuring Mixed FPGA Daisy Chains," Jun. 1, 1996, (Version 1.0), pp. 14-33 to14-34. |
Alfke, P., "Dynamic Reconfiguration," Jun. 1, 1996, (Version 1.0), pp. 14-39 to14-40. |
Bournemouth University Page of Dynamically Reconfigurable Hardware, at http://dec.bournemouth.ac.uk/dec.sub.-- ind/decind6/drhw.sub.-- page.htm on Jan. 9, 1998. |
XC6200 Field Programmable Gate Arrays, (Version 1.10) Apr. 24, 1997,pp. 1-12. |
FPGA Configuration E.sup.2 PROM Memory: 512K and 1M, ATMEL, Dec. 1997, pp. 1-9. |