Patent Application
20240221692
This application claims the priority benefit of Taiwan application serial no. 111150877, filed on Dec. 30, 2022. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The disclosure relates to a display apparatus and a driving method of a display panel, and in particular, to an e-paper display apparatus and a driving method of an e-paper display panel.
Generally, the way to drive an e-paper display panel to display an image screen is to turn on a gate line, and write a data signal in sequence into a pixel circuit so as to drive the pixel circuit to display the respective image data. The gate line is configured to control the turn-on state of the transistor elements of the same pixel row, and a driver circuit controls each pixel row to turn on in sequence so as to drive the e-paper display panel to display the image screen.
In the conventional technology, in addition to the gate line, the e-paper display panel may further include a gate selection line due to different pixel design methods. However, in the structure in which a gate line is configured with a gate selection line, the stray capacitance of the e-paper display panel circuit increases, thereby increasing the driving load of the driver circuit, and the driving voltage for driving the gate line also needs to be increase to maintain the charge rate.
The disclosure provides an e-paper display apparatus and a driving method of an e-paper display panel, which may reduce the driving voltage and the stray capacitance of the circuit, thereby reducing the power consumption.
An e-paper display apparatus of the disclosure includes an e-paper display panel including multiple source lines, multiple gate selection lines, and multiple pixel circuits and a driver circuit coupled to the e-paper display panel and configured to output a driving signal to the gate selection line. The gate selection lines and the source lines are disposed along a first direction. The source lines corresponding to the gate selection line simultaneously receive respective data signals when the gate selection line is turned on. The driving signal includes a first period and a second period. The gate selection line is turned on during the first period, and the gate selection line is turned off during the second period. A time length of the first period is greater than a time length of the second period.
In an embodiment of the disclosure, the time length of the above-mentioned first period is T1, and T1 conforms to (1/f/GL)<T1<(1/f/GL)×2, where f is the frame rate of the e-paper display panel, and GL is the number of pixel circuits arranged in the first direction.
In an embodiment of the disclosure, the time length T1 of the above-mentioned first period conforms to (1/f/GL)×1.5<T1<(1/f/GL)×2.
In an embodiment of the disclosure, the above-mentioned e-paper display panel further includes multiple gate lines. The pixel circuits are electrically connected to the respective gate line and the respective source line, and the gate selection lines are electrically connected to the corresponding gate line.
In an embodiment of the disclosure, each of the above-mentioned pixel circuits includes a transistor element, and the transistor element is an oxide thin-film transistor.
In an embodiment of the disclosure, the number of the gate selection lines is less than the number of the source lines.
In an embodiment of the disclosure, each gate selection line is disposed between the corresponding two adjacent source lines among the source lines.
A driving method of an e-paper display panel of the disclosure is provided hereafter. A driving signal is output to multiple gate selection lines of the e-paper display panel. The gate selection lines and source lines are disposed along a first direction. The respective data signals are simultaneously output to the source lines corresponding to the gate selection line when the gate selection line is turned on.
In an embodiment of the disclosure, the above-mentioned driving signal includes a first period and a second period. The steps of outputting the driving signal to the gate selection line of the e-paper display panel are provided hereafter. The gate selection line is turned on during the first period. The gate selection line is turned off during the second period.
In order to make the above-mentioned features and advantages of the disclosure clearer and easier to understand, the following specific embodiments are described in detail together with the accompanying drawings.
The e-paper display panel 110 includes multiple gate lines G1 and G2, multiple source lines S1, S2, S3, S4, S5, and S6, multiple gate selection lines G1_SEL and G2_SEL, and multiple pixel circuits 112. The source lines S1, S2, S3, S4, S5, and S6 and the gate selection lines G1_SEL and G2_SEL are disposed along a first direction (vertical direction), and arranged along a second direction (horizontal direction). The pixel circuits 112 are electrically connected to the respective gate line and the respective source line. The gate selection lines are electrically connected to the corresponding gate line. Each gate selection line is disposed between the corresponding two adjacent source lines among the multiple source lines. In the embodiment, the number of gate selection lines is less than the number of source lines. The number of gate selection lines is equal to the number of gate lines.
For example, the pixel circuit 112_0 is electrically connected to the gate line G1 and the source line S1. The gate selection line G1_SEL is electrically connected to the gate line G1. The gate selection line G1_SEL is disposed between the corresponding two adjacent source lines S2 and S3 among the source lines S1, S2, S3, S4, S5, and S6, and no pixel circuit is disposed between the corresponding two adjacent source lines S2 and S3. The gate selection line G2_SEL is electrically connected to the gate line G2. The gate selection line G2_SEL is disposed between the corresponding two adjacent source lines S4 and S5 among the source lines S1, S2, S3, S4, S5, and S6. In addition, in the embodiment, the gate selection line G1_SEL is electrically insulated from the gate line G2, and the gate selection line G2_SEL is electrically insulated from the gate line G1.
In addition, the multiple source lines among the source lines S1, S2, S3, S4, S5, and S6 are included between the two adjacent gate selection lines G1_SEL and G2_SEL among the gate selection lines. For example, the source lines S3 and S4 are included between the two adjacent gate selection lines G1_SEL and G2_SEL.
In the embodiment, since the two adjacent source lines are provided with a gate selection line, the number of gate selection lines is less than the number of source lines. Therefore, compared with the structure in the conventional technology in which a gate line is configured with a gate selection line, the stray capacitance of the e-paper display panel circuit may be reduced, such that the power consumption and the border range around the e-paper display panel 110 may be further reduced. In addition, the number of elements and the number of signal lines in
On the other hand, each pixel circuit 112 includes a storage capacitor Cst and a transistor element SW1 or SW2, and the transistor element SW1 or SW2 may be used as a switch element. The transistor element SW1 or SW2 is implemented as an oxide thin-film transistor, for example, and the structure thereof includes a channel layer. The material of the channel layer is oxide, such as indium gallium zinc oxide (IGZO) or indium zinc tin oxide (IZTO). The material of the above-mentioned channel layer is used for illustration only, and is not intended to limit the disclosure.
The driver circuit 120 is configured to output the driving signal 130 to the gate selection lines G1_SEL and G2_SEL so as to drive the e-paper display panel 110 to display the image screen.
The driving signal 130 shown in
Specifically, in the embodiment, when the gate selection line G1_SEL is turned on, the source lines S1 to S6 corresponding to the gate selection line G1_SEL simultaneously receive the respective data signals. Taking the adjacent source lines S2 and S3 as an example, the gate selection line G1_SEL is disposed between the two adjacent source lines S2 and S3. The data signals are respectively written into the pixel circuits 112_1 (first pixel circuit) and 112_2 (second pixel circuits) among the pixel circuits 112 from the two adjacent source lines S2 and S3, and the pixel circuits 112_1 and 112_2 are not adjacent. The pixel circuits 112_1 and 112_2 are located in different pixel columns and pixel rows.
Next, when the gate selection line G2_SEL is turned on, the source lines S1 to S6 corresponding to the gate selection line G2_SEL simultaneously receive the respective data signals. Taking the adjacent source lines S4 and S5 as an example, the gate selection line G2_SEL is disposed between the two adjacent source lines S4 and S5. The data signals are respectively written into the pixel circuits 112_3 and 112_4 from the two adjacent source lines S4 and S5, and the pixel circuits 112_3 and 112_4 are not adjacent. The pixel circuits 112_3 and 112_4 are located in different pixel columns and pixel rows.
In the embodiment, the gate selection line between two adjacent source lines is configured to control the pixel circuits in different columns, so that compared with the structure in the conventional technology in which a gate line is configured with a gate selection line, the turn-on time T1 may be extended, such that the charging time of the pixel circuit may be prolonged and the driving voltage (i.e., the gate voltage) for driving the gate selection line and the gate line may be reduced.
In detail, in
Therefore, the time length T1 of the first period is (1/f/GL)×2 minus the RC delay time, so the time length T1 of the first period is less than (1/f/GL)×2, but greater than the turn-on time (1/f/GL) of the conventional technology. In another embodiment, the time length T1 of the first period conforms to (1/f/GL)×1.5<T1<(1/f/GL)×2.
To sum up, in the embodiment of the disclosure, since the two directly adjacent source lines are provided with only a gate selection line, the number of gate selection lines is less than the number of source lines. Therefore, compared with the structure in the conventional technology in which a gate line is correspondingly configured with a gate selection line, the stray capacitance of the e-paper display panel circuit may be reduced, such that the power consumption and the border range around the e-paper display panel may be further reduced. In addition, using the gate selection line located between the two adjacent source lines to control the pixel circuits in different columns may extend the turn-on time of the gate selection line, prolong the charging time of the pixel circuit, and reduce the driving voltage for driving the gate selection line and the gate line.
Although the disclosure has been described with reference to the embodiments above, the embodiments are not intended to limit the disclosure. Any person skilled in the art can may make some changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of the disclosure will be defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 111150877 | Dec 2022 | TW | national |
