This project is jointly supported by NSF, Estonian Research Council (ETAG), and US National Academy of Sciences. The research will be conducted in multilateral partnership uniting Carnegie Melon University (US), Tallinn University of Technology (Estonia), and V.N.Karazin Kharkiv National University (Ukraine). US part of the international research team is co-funded by NSF OISE/OD and CISE/CNS. <br/><br/>Cryptographic algorithms allow us to send secret messages over an otherwise insecure communication channel, such as the internet. These algorithms are extremely important since they enable several aspects of our digital lives, be it online banking, messaging services, mobile phone networks, and many more. To realize such protected communications and maintain the privacy of the parties talking to each other, government agencies set cryptographic standards for adoption. These standards serve as a common language for two devices to talk to one another while keeping the content of the exchange messages protected. For instance, in the US, the National Institute of Standards and Technology (NIST) recommends, among others, the Advanced Encryption Standard (AES) for encryption/decryption in civilian communication. AES was chosen after a long competition where many candidates were considered and AES came out as the winning algorithm. Today, there are hundreds of implementations of AES in software form or in pure hardware form, i.e., implemented as a computer chip.<br/> <br/>Outside the US, many other standards exist. In Ukraine, a competition was also held which culminated in 2015 with the selection of Kalyna and Kupyna as the national standards. The existing software implementations of Kalyna and Kupyna have performance and security level comparable to their US counterparts. However, there is no known hardware architecture for the design of Kalyna or Kupyna. There is a need for Kalyna/Kupyna-capable hardware that displays (i) high performance; (ii) low power; (iii) tamper resistance; (iv) small footprint; and (v) physical security. This is the technical goal of this EAGER award, i.e., to execute a broad design space and security space exploration for the implementation of a block cipher (Kalyna) and a hash algorithm (Kupyna). This EAGER project represents a study on how to best implement these algorithms in a computer chip. The research team includes chip designers from the US and from Estonia, as well cryptography experts from Ukraine. The main technical outcome of the project is one fabricated chip containing several variants of the Kalyna and Kupyna algorithms. <br/><br/>This EAGER award also has dissemination goals. Knowingly, the country of Ukraine does not enjoy access to trusted chip fabrication technology. Chip design knowledge is also scarce. We strive to have Ukrainian universities teaching, in the near future, both software and hardware cryptographic engineering. The latter is specific knowledge that, today, is not adequately covered by any university in the country. In order to achieve this goal, the chip design tasks executed in this project will be highly reproducible: design resources will be openly shared on public repositories, including Verilog source files. Synthesis scripts for state-of-the-art commercial chip design tools will also be shared. Finally, the entire design process will be documented in order to showcase the entire concept of the Kalyna/Kupyna chip, step by step, from RTL to layout. This documented effort will be made openly available to the chip design and cryptographic communities at large.<br/><br/>This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.