NSF Award
1457506
This project will explore the application of heterogeneous memory architectures to reduce power consumption while maintaining adequate response times in embedded computer systems. The slower response times of memory devices as compared to the speeds of processing elements is recognized as a major performance bottleneck. Power used by memory devices, especially static power, is recognized as a major source of energy consumption in computers. There are a variety of different types of memory technologies, each occupying a discrete point in a multidimensional trade-off space represented by parameters such as memory access latency, memory bandwidth, power consumption, memory lifetime, and cost of memory devices. Heterogeneous memory systems represent a potentially transformative development because combining several different types of memory opens up a much broader range of this trade-off space. The focus of this preliminary study is on efficient use of heterogeneous memory types in a scratch-pad memory. Expected outcomes include: 1) A new heterogeneous memory hierarchy that integrates on-chip Static Random Access Memory (SRAM), Magnetic Random Access Memory (MRAM), Zero-capacitor RAM (Z-RAM) technologies, as well as off-chip DRAM. 2) a set of algorithms that achieve allocation for optimal memory access speed or efficient space utilization. 3) a simulation toolkit that integrates commonly used simulation benchmarks, such as MiBench, PARSEC, and MediaBench.<br/><br/>The broader impacts of this research include potential for contributing technology that reduces energy consumption for current embedded computing applications, and may enable more advanced future embedded computing systems within energy, power, and thermal dissipation constraints. The project will integrate research with graduate education, both in the classroom and through direct participation of students in the research. It will include collaborations with researchers at IBM, Pacific Northwest Laboratories, and Intel.
