Claims
- 1. In a line driver/receiver circuit where the line driver is connected with its output terminals to a load for supplying a transmit signal thereto and where the receiver is connected with its input terminals to the load for simultaneously receiving a receive signal therefrom, an arrangement for canceling the transmit signal on the input terminals of the receiver, the output terminals of the line driver being connected to the load via equal first impedances, the input terminals of the receiver being connected to the load via equal first resistors and to respective output terminal of the line driver via equal second resistors, wherein
the first impedances are complex impedances to match the load impedance and are of an impedance value that is much smaller than the impedance value of the load impedance, and transconductance amplifiers are provided to sense the voltage across the first impedances and supply corresponding currents to respective input terminal of the line driver.
- 2. The circuit according to claim 1, wherein a drive/termination impedance of the line driver equals the impedance value of one of the impedances multiplied by k, wherein k is a function of the line driver gain and the transconductance amplifier gains.
- 3. An echo canceling arrangement comprising:
a line driver having two inputs and two outputs, a load coupled with the outputs of the line driver via first and second impedances, a line receiver having two inputs, wherein the inputs are coupled through a network with the load and the outputs of said line driver, first and second transconductance amplifiers having two inputs and an output, wherein the inputs of the first transductance amplifier are coupled with the first impedance and its output with the one input of the line driver and the inputs of the second transductance amplifier are coupled with the second impedance and its output with the other input of the line driver, wherein the first impedances are complex impedances to match the load impedance and are of an impedance value that is much smaller than the impedance value of the load impedance.
- 4. The echo canceling arrangement according to claim 3, wherein the network comprises:
a first resistor coupled between one input of the line receiver and the load, a second resistor coupled between the one input and one output of the line driver, a third resistor coupled between the other input of the line receiver and the load, and a fourth resistor coupled between the other input and the other output of the line driver.
- 5. The echo canceling arrangement according to claim 3, wherein the first and third resistor are equal and the second and fourth resistor are equal.
- 6. The echo canceling arrangement according to claim 3, wherein a drive/termination impedance of the line driver equals the impedance value of one of the impedances multiplied by k, wherein k is a function of the line driver gain and the transconductance amplifier gains.
- 7. An asymetric digital subscriber line (ADSL) driver receiver circuit comprising:
an ADSL driver having two inputs and two outputs, a load coupled with the outputs of the driver via first and second impedances, an ADSL receiver having two inputs, wherein the inputs are coupled through a network with the load and the outputs of said driver, first and second transconductance amplifiers having two inputs and an output, wherein the inputs of the first transductance amplifier are coupled with the first impedance and its output with the one input of the driver and the inputs of the second transductance amplifier are coupled with the second impedance and its output with the other input of the driver, wherein the first impedances are complex impedances to match the load impedance and are of an impedance value that is much smaller than the impedance value of the load impedance.
- 8. The circuit according to claim 7, wherein the network comprises:
a first resistor coupled between one input of the receiver and the load, a second resistor coupled between the one input and one output of the driver, a third resistor coupled between the other input of the receiver and the load, and a fourth resistor coupled between the other input and the other output of the driver.
- 9. The circuit according to claim 7, wherein the first and third resistor are equal and the second and fourth resistor are equal.
- 10. The circuit according to claim 7, wherein a drive/termination impedance of the driver equals the impedance value of one of the impedances multiplied by k, wherein k is a function of the driver gain and the transconductance amplifier gains.
Priority Claims (1)
Number |
Date |
Country |
Kind |
SE0103414-9 |
Oct 2001 |
SE |
|
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application is a continuation of copending International Application No. PCT/SE02/0168 filed Sep. 18, 2002 which designates the United States, and claims priority to Swedish application no. 0103414-9 filed Oct. 11, 2001.
Continuations (1)
|
Number |
Date |
Country |
Parent |
PCT/SE02/01688 |
Sep 2002 |
US |
Child |
10821781 |
Apr 2004 |
US |