Echo Preventing Circuit and Digital Signal Processing Circuit

Abstract

An echo preventing circuit comprises a filter that is inputted with a first digital signal and outputs a second and a third digital signals; a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal; a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal; an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal; a subtracting circuit that outputs a fourth analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal; and an AD converter that converts the fourth analog signal into a fourth digital signal and outputs the fourth digital signal, wherein the filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and wherein the fourth analog signal outputted from the subtracting circuit is outputted as an output signal corresponding to the third analog signal.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

For more thorough understanding of the present invention and the advantages thereof, the following description should be referenced in conjunction with the accompanying drawings, in which:

FIG. 1 depicts a block diagram of a first embodiment of an echo preventing circuit and a digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 2 depicts paths A and B of the echo preventing circuit shown in FIG. 1;

FIG. 3 depicts a diagram of the case where an earphone microphone 18 is included in the path A shown in FIG. 2;

FIG. 4A depicts an impulse response of the path A shown in FIG. 2 or 3;

FIG. 4B depicts an impulse response of the path B shown in FIG. 2 or 3;

FIG. 5 depicts a part of the configuration of a DSP 2;

FIG. 6 depicts another part of the configuration of the DSP 2;

FIG. 7 depicts another example of FIR filters 4 and 11;

FIG. 8 depicts a flowchart of a process operation of an echo preventing circuit and a digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 9 depicts a block diagram of a second embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 10 depicts a block diagram of a third embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 11 depicts a block diagram of a fourth embodiment of an echo preventing circuit and a digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 12 depicts paths C and D of the echo preventing circuit shown in FIG. 11;

FIG. 13 depicts a block diagram of a fifth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 14 depicts a block diagram of a sixth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 15 depicts a block diagram of a seventh embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 16 depicts a diagram of paths E and F of the echo preventing circuit shown in FIG. 15;

FIG. 17 depicts a block diagram of a eighth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 18 depicts a block diagram of a ninth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 19 depicts a block diagram of a tenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 20 depicts paths G and H of the echo preventing circuit shown in FIG. 19;

FIG. 21 depicts a block diagram of a eleventh embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 22 depicts a block diagram of a twelfth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 23 depicts a block diagram of a thirteenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 24 depicts paths I and J of the echo preventing circuit shown in FIG. 23;

FIG. 25A depicts an impulse response of the path I shown in FIG. 24;

FIG. 25B depicts an impulse response of the path J shown in FIG. 24;

FIG. 26 depicts a part of the configuration of a DSP 202;

FIG. 27 depicts a block diagram of the configuration of an ARMA filter 300 shown as an example of a digital filter 211;

FIG. 28 depicts a flowchart of a process operation in the thirteenth embodiment;

FIG. 29 depicts a block diagram of a fourteenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 30 depicts a block diagram of a fifteenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 31 depicts a block diagram of a sixteenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 32 depicts paths K and L of the echo preventing circuit shown in FIG. 31;

FIG. 33 depicts a block diagram of a seventeenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 34 depicts a block diagram of a eighteenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 35 depicts a block diagram of a nineteenth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 36 depicts paths M and N of the echo preventing circuit shown in FIG. 35;

FIG. 37 depicts a block diagram of a twentieth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 38 depicts a block diagram of a twenty-first embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 39 depicts a block diagram of a twenty-second embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 40 depicts paths O and P of the echo preventing circuit shown in FIG. 39;

FIG. 41 depicts a block diagram of a twenty-third embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 42 depicts a block diagram of a twenty-fourth embodiment of the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 43 schematically depicts a mobile phone 19 applied with the echo preventing circuit and the digital signal processing circuit included in the echo preventing circuit, according to the present invention;

FIG. 44 depicts a block diagram of a first application of the echo preventing circuit according to the present invention;

FIG. 45 depicts a block diagram of a second application of the echo preventing circuit according to the present invention;

FIG. 46 depicts a block diagram of an exemplary configuration of an echo preventing circuit 41b in the second application;

FIG. 47 depicts a block diagram of a third application of the echo preventing circuit according to the present invention;

FIG. 48 depicts a block diagram of an exemplary configuration of an echo preventing circuit 4cb in the third application;

FIG. 49 depicts a block diagram of another application of the echo preventing circuit according to the present invention;

FIG. 50 depicts a block diagram of another application of the echo preventing circuit according to the present invention; and

FIG. 51 depicts a conventional echo preventing circuit.

Claims

1. An echo preventing circuit comprising: a filter that is inputted with a first digital signal and outputs a second and a third digital signals;a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal;a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal;an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal;a subtracting circuit that outputs a fourth analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal; andan AD converter that converts the fourth analog signal into a fourth digital signal and outputs the fourth digital signal, whereinthe filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and whereinthe fourth analog signal outputted from the subtracting circuit is outputted as an output signal corresponding to the third analog signal.

2. The echo preventing circuit of claim 1, further comprising a switching circuit that can selectively output the fourth analog signal or a fifth analog signal, whereinthe switching circuit outputs the fourth analog signal to the AD converter when the filter coefficients of the filter are set, and whereinthe switching circuit outputs the fifth analog signal to the AD converter to cause the AD converter to generate the first digital signal by analog/digital-converting the fifth analog signal when the output signal corresponding to the third analog signal is outputted.

3. An echo preventing circuit comprising: a filter that is inputted with a first digital signal and outputs a second and a third digital signals;a first DA converter that converts the second digital signal into a first analog signal and outputs the first analog signal;a second DA converter that converts the third digital signal into a second analog signal and outputs the second analog signal;an input/output terminal that outputs the first analog signal or that is inputted with a third analog signal;a subtracting circuit that outputs a fourth analog signal obtained by subtracting the second analog signal from a signal formed by combining the first analog signal and the third analog signal; andan AD converter that converts the fourth analog signal into a fourth digital signal and outputs the fourth digital signal, whereinthe filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and whereinthe fourth digital signal outputted from the AD converter is outputted as an output signal corresponding to the third analog signal.

4. The echo preventing circuit of claim 3, further comprising a first switching circuit that can select whether the first analog signal is outputted to the input/output terminal and the subtracting circuit or the first analog signal is outputted as an output signal; anda second switching circuit that can selectively output the fourth analog signal or a sixth analog signal, whereinthe filter converts the first digital signal into the second digital signal and outputs the second digital signal to the first DA converter, when an earphone microphone that converts the first analog signal into sound and outputs the sound and converts sound inputted thereinto into the third analog signal and outputs the third analog signal is connected to the input/output terminal, whereinthe filter outputs the first digital signal as the second digital signal, when the earphone microphone is not connected to the input/output terminal, whereinthe first switching circuit outputs the first analog signal to the input/output terminal and the subtracting circuit, when the earphone microphone is connected to the input/output terminal, whereinthe first switching circuit outputs the first analog signal as an output signal, when the earphone microphone is not connected to the input/output terminal, whereinthe second switching circuit outputs the fourth analog signal to the AD converter, when the earphone microphone is connected to the input/output terminal, and whereinthe second switching circuit outputs the sixth analog signal to the AD converter to cause the AD converter to generate the fourth digital signal by converting the sixth analog signal thereinto, when the earphone microphone is not connected to the input/output terminal.

5. The echo preventing circuit of claim 4, further comprising a detecting circuit that detects the connection state of the earphone microphone to the input/output terminal and outputs the detection signal, whereinthe filter converts the first digital signal into the second digital signal and outputs the second digital signal to the first DA converter, when the earphone microphone is connected to the input/output terminal, based on the detection signal, whereinthe filter outputs the first digital signal to the first DA converter as the second digital signal, when the earphone microphone is not connected to the input/output terminal, based on the detection signal, whereinthe first switching circuit outputs the first analog signal into the input/output terminal and the subtracting circuit, when the earphone microphone is connected to the input/output terminal, based on the detection signal, whereinthe first switching circuit outputs the first analog signal as an output signal, when the earphone microphone is not connected to the input/output terminal, based on the detection signal, whereinthe second switching circuit outputs the fourth analog signal to the AD converter, when the earphone microphone is connected to the input/output terminal, based on the detection signal, and whereinthe second switching circuit outputs the sixth analog signal to the AD converter to cause the AD converter to generate the fourth digital signal by converting the sixth analog signal thereinto, when the earphone microphone is not connected to the input/output terminal, based on the detection signal.

6. A digital signal processing circuit comprising: a first input terminal that is inputted with a first digital signal;a filter that is inputted with the first digital signal from the first input terminal and outputs a second and a third digital signals;a first DA converter that converts the second digital signal into and outputs a first analog signal;a second DA converter that converts the third digital signal into and outputs a second analog signal;a first output terminal that outputs the first analog signal;a second output terminal that outputs the second analog signal;a second input terminal that is inputted with a fourth analog formed by subtracting the second analog signal from the second output terminal from a signal formed by combining the first analog signal from the first output terminal and a third analog signal on an input/output signal shared line;an AD converter that converts the fourth analog signal into and outputs a fourth digital signal; anda third output terminal that outputs the fourth digital signal, whereinthe filter sets filter coefficients for which the fourth analog signal is a signal formed by removing or attenuating the first analog signal from a signal formed by combining the first analog signal and the third analog signal, based on the fourth digital signal outputted from the AD converter when signals are inputted into the first and the second DA converters while the third analog signal is not present, and whereinthe fourth digital signal outputted from the third output terminal is outputted as an output signal corresponding to the third analog signal.

7. The digital signal processing circuit of claim 6, further comprising a third input terminal that is inputted with a detection signal indicative of the connection state to the input/output terminal of an earphone microphone that converts the first analog signal into and outputs sound and that converts sound inputted thereinto into and outputs the third analog signal, whereinthe filter converts the first digital signal into and outputs the second digital signal to the first DA converter, when the earphone microphone is connected to the input/output terminal, based on the detection signal, and whereinthe filter outputs the first digital signal to the first DA converter as the second digital signal, when the earphone microphone is not connected to the input/output terminal, based on the detection signal.