Patent Application
20120249851
The present invention relates generally to semiconductor imagers. More specifically, the present invention relates to an anti-eclipse (AE) circuit for imagers.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, a photoconductor or a photodiode for accumulating photo-generated charge in a specified portion of a substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion (FD) region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing the charge at the storage region. Photo-charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
The states of the transfer and reset transistors 111, 112 determine whether the floating diffusion region C is coupled to the light sensitive element 101 for receiving photo generated charge generated by the light sensitive element 101 during a charge integration period, or a source of pixel power VAA from node A during a reset period.
The pixel 100 is operated as follows: The SEL control signal is asserted to cause the row select transistor 114 to conduct. At the same time, the RS control signal is asserted while the TX control signal is not asserted. This couples the floating diffusion region C to the pixel power VAA at node A, and resets the voltage at node C to the an initial voltage. The pixel 100 outputs a reset signal VRST to the load circuit 120. Node B is coupled between the row select transistor 114 and the load circuit 120 and serves as an input to a sample and hold circuit (not shown) that samples and holds the pixel reset voltage VRST.
After the reset signal VRST has been output, the RS control signal is de-asserted. The light sensitive element 101 has been exposed to incident light and accumulates charge on the level of the incident light during a charge integration period. After the charge integration period and the output of the signal VRST, the TX control signal is asserted. This couples the floating diffusion region C to the light sensitive element 101. Charge flows through the transfer transistor 111 and diminishes the voltage at the floating diffusion region C. The pixel 100 outputs a photo signal VSIG to the load circuit 120 which appears at node B and is sampled by the sample and hold circuit (not shown). The reset and photo signals VRST, VSIG, are different components of the overall pixel output (i.e., Voutput=VRST−VSIG).
A pixel 100 is susceptible to a type of distortion known as eclipsing. Eclipsing refers to distortion arising when a pixel outputs a signal corresponding to a dark pixel even though bright light is incident upon the pixel. Eclipsing can occur when a pixel is exposed to bright light, as the light sensitive element 101 can produce a large quantity of photogenerated charge. While the pixel 100 is outputting the reset signal VRST, a portion of the photogenerated charge produced by the light sensitive element 101 during an ongoing integration period may spill over the transfer transistor 111 into the floating diffusion node C. This diminishes the reset voltage at the floating diffusion node and can cause pixel 100 to output an incorrect (i.e., diminished voltage) reset signal VRST. This, in turn, can cause the reset and photo signals VRST, VSIG, to be nearly the same voltage. For example, the photo and reset signals VRST, VSIG, may each be approximately 0 volts. The pixel output (VRST−VSIG) can, therefore, become approximately 0 volts, which corresponds to an output voltage normally associated with a dark pixel.
An anti-eclipse circuit can be used to minimize the effect of eclipsing. For example, since during eclipse a pixel's reset voltage tends to drop towards zero volts, an anti-eclipse circuit can monitor the voltage level of the reset signal. If the voltage level drops below a threshold voltage, the anti-eclipse circuit can assume that the eclipsing may occur (or is occurring) and then correct the voltage level of the reset signal by pulling the reset level up to a correction voltage, thereby minimizing the eclipsing effect.
U.S. Pat. No. 6,873,363, which issued on Mar. 29, 2005, describes flagging oversaturated pixels in an active pixel sensor (APS). This patent is incorporated herein by reference in its entirety. Various portions of the patent are described below:
As described therein, a saturation flag can be used to identify oversaturated pixels and replace the value read out from an oversaturated pixel with a predetermined maximum value corresponding to a maximum brightness for the pixel in the image. This removes the artifacts in the resulting image, and the pixels in the APS array that receive the most light appear brightest in the images that are produced.
At high incident light level 202, a photodiode becomes unable to absorb additional photons during the integration period and saturates. According to the description in the referenced patent, a saturation flag is set if the photodiode is saturated.
As shown in
Thus, each of the signals read out from pixels receiving incident light levels greater than incident light level 204 in Region I is replaced with a maximum digital value. Accordingly, the corresponding pixels in the image are the brightest.
At zero incident light level 200, signal voltage S equals reset voltage R. Consequently the difference voltage (R−S) equals zero. The sensor reads a zero value as indicating that the pixel has received no incident light. A zero value produces a black pixel in the resultant image. In Region I, signal voltage S is strongly responsive to the incident light level. As the light level increases, signal voltage S decreases while reset voltage R remains relatively constant. Thus, the difference voltage (R−S) increases, causing the pixel to brighten. Region I corresponds to a photodetector's active region.
Ideally, reset voltage R is constant. However, as shown in Region II of
In Region II, reset voltage R gradually drops while signal voltage S remains constant at Vsat. Consequently, the difference voltage (R−S) continues to drop with increasing light levels. In a conventional CMOS imager, the increasingly oversaturated pixel, which should appear to brighten in the image, actually reads out as a darkening pixel.
As shown in Region III, at an extremely high light level 206, reset voltage R will also saturate at Vsat and the difference voltage (R−S) will equal zero, representing a black pixel. Regions of such oversaturated pixels produce artifacts in conventional CMOS imagers.
Continuing description of the referenced patent, pixels exposed to light levels above light level 204 in Region I of
It will be appreciated that this anti-eclipse (AE) scheme is based on clamping the pixout voltage so that it does not drop below a certain level during reset sampling. The AE voltage setting, however, has to be high enough so that the signal chain saturates for brightly lit pixels, but not so high that it interferes with the pixel reset level when the pixel is not eclipsing.
If a pixel is brightly lit, charge accumulated in the floating diffusion (FD) between the reset pulse and reset sampling (SHR) can lower the sampled reset level. If the reset level drops sufficiently before it is sampled, the pixel output will not have sufficient swing left to saturate the ADC, when the signal is sampled after the transfer (TX). Eclipse occurs as dark areas in strongly saturated images (e.g. the center of the sun) become grey or black.
If the AE setting is too high, the AE clamp will affect the reset sampling even when the pixel is not in saturation, thereby destroying the double correlated sampling (CDS). Due to transistor threshold variation between clamping devices, some turn on too soon, causing column fixed pattern noise (FPN) in the image.
If the AE setting is too low, the signal chain does not saturate, and brightly lit areas become grey (weak eclipse). Due to threshold variation in AE clamp circuits, the grey areas will have stripes.
Unfortunately, with a lower reset level (as seen in high conversion gain pixels and soft FD reset (IR) pixels), there is less and less room for setting the AE voltage so that it does not destroy CDS while still saturating the signal chain. The present invention, as will be explained, uses the ADCs to detect eclipse, while avoiding the high clamping levels.
The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and show by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized, and that structural, logical, and electrical changes may be made without departing from the spirit and scope of the present invention. The progression of processing steps described is exemplary of embodiments of the invention; however, the sequence of steps is not limited to that set forth herein and may be changed as is known in the art, with the exception of steps necessarily occurring in a certain order.
The term “pixel,” as used herein, refers to a photo-element unit cell containing a photosensor and associated transistors for converting photons to an electrical signal. For purposes of illustration, a small number of representative pixels are illustrated in the figures and description herein: however, typically fabrication of a large plurality of like pixels proceeds simultaneously. Accordingly, the following detailed description is not to be taken in a limiting sense; and the scope of the present invention is defined only by the appended claims.
In addition, although the invention is described below with reference to a CMOS imager, the invention has applicability to any solid state imaging device having a storage node which is reset and then has charges transferred to it. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
Eclipse occurs when a pixel is so brightly lit that the floating diffusion (FD) is discharged significantly between the release of a reset (RST) pulse and the end of sampling. Due to the resulting drop in the pixel output (pixout) voltage towards the end of reset sampling (SHR), the difference between sampled voltages at SHR and signal sampling (SHS) is not enough to saturate the ADC, and pixels which should be read out as white become grey, or black.
As will be explained, the present invention uses one ADC clock cycle to compare the pixout voltage after reset A/D conversion, but before transfer (TX) to a digital threshold. In this manner, the present invention senses whether the pixel reset level is changing due to an eclipse condition (over-saturated photodetector blooming into the FD). This removes the need to saturate the signal chain during eclipse and allows a lowering of the pixout clamp voltage to a safe level. The decision from the extra ADC clock cycle is read out to the digital section to determine whether a pixel is eclipsing or not.
Now referring to the figures, where like numerals designate like elements,
The S/H circuits 72 are connected to the column lines 22 of the array 56. The analog-to-digital converters 60 are connected to the S/H circuits 72 by what is commonly known as a column-parallel architecture. That is, in the illustrated imaging device 500, each column or column line 22 of the array 56 is connected to a respective analog-to-digital converter 60, which operate in parallel to convert analog signals from the array 56 (via the S/H circuitry 72) to digital signals.
The imaging device 500 is operated by the row operations and ADC controller 58, which controls the row driver 54 and the analog-to-digital converters 60. The row operations and ADC controller 58 also issues a sample control signal SAMPLE to the first memory bank 62, which is illustratively an SRAM device. The second controller, i.e., the SRAM/read controller 66 also controls the operation of the imaging device 50 by controlling the second memory bank 64, also an SRAM device (via a shift control signal SHIFT), and the column decoder 70.
In operation, row lines are selectively activated by the row driver 54 in response to the row decoder 52. The S/H circuits 72 input a pixel reset signal Vrst and a pixel image signal Vsig for selected pixels. A differential signal is produced, by a differential amplifier within the S/H circuits 72, for each pixel and is digitize d by the analog-to-digital converters 60. The digitizing of the data from each column is performed in parallel. The digitized signals are stored in the first memory bank 62 (when the sample control signal SAMPLE is issued) and subsequently shifted into the second memory bank 64. the sense amplifier circuitry 68 senses the stored digital data from the second memory bank 64 and outputs the digital information so that it may be processed by e.g., an image processor (not shown).
Turning next to
The pixel output signal from column 508a is connected to column amplifier 540a, successive approximation register (SAR), analog-to-digital converter (ADC) 545a and column memory register 546a. The SAR ADC includes comparator 547 which provides an output (cmp_out) to a SAR digital-to-analog (DAC), the latter generally designated as 548. The DAC 548 runs a sequence based on the comparator output. It will be appreciated that the DAC is a parallel DAC and runs one cycle per bit to obtain a final digital output signal, adc_dout.
The Vrefhi and Vreflo are the upper and lower reference voltages (towards which the ADC compares an incoming pixel value). The difference between them indicates the full-scale input range of the ADC.
The sel<11:0> in the example shown in
The set and reset controls are used to pre-set bits in the DAC to known values. Typically, before conversion begins, (a) the ADC comparator (which may be seen as a high-gain OTA in an open loop) is reset to remove any inherent offset and (b) the DAC is reset to a known value. The former ((a)) is done when adc_cmp_rst signal is asserted, which shorts inputs and outputs of the comparator during the beginning of signal sampling, and releases them before ADC conversion begins. The latter ((b)) is done by setting all the sel<11:0> signals, in order to address the whole DAC while applying the reset signal. This connects all the DAC capacitors to the Vreflo (as an example).
Cycling through the DAC bit by bit, starting with the MSB, the capacitors are connected to Vrefhi, one by one and, depending on the following comparator output, either moved back to Vreflo or left at Vrefhi. A capacitor is connected to Vrefhi by asserting both the sel signal and the set signal. After the comparator has completed a comparison, the result is written to the DAC's control latch for the bit, selecting to which voltage the DAC capacitor should be connected. At this point, the respective sel signal is still high. In addition, the sel<11:0> bus can be used to intentionally reset or re-write a particular bit by selecting the bit's address and the set or reset signal. This feature can be used to pre-program a threshold into the DAC for detecting eclipse.
It will be understood that the ADC described in
Turning next to
It will be understood that column amplifiers are not required and may be omitted from each of the columns 508e and 508f, as shown in
Still referring to
The ADC's digital control logic & bias, generally designated as 551 in
The SHX controls sampling switch 632, as shown in
The ADC_CMP_RST signal resets the ADC's comparator 547, as shown in
It will be understood that
The reset sampling (SHR) phase and the signal sampling (SHS) phase will now be described, including an anti-eclipse sampling (AE) phase, with reference to the timing diagrams shown in
(1) PIXOUT (pixel output);
(2) FD (floating diffusion signal);
(3) RST (reset control);
(4) TX (transfer control);
(5) ADC_CMP_RST (ADC comparator reset control);
(6) SHX (reset sampling control, signal sampling control, and AE sampling control (the latter shown in FIGS. 9 and 10));
(7) ADC_CLK (clocking signal controlling timing of the ADC);
(8) A/D (converted reset signal SHR), converted signal (SHS), and converted AE signal (shown in FIGS. 9 and 10)); and
(9) clamp control, shown in
Referring first to
It will be understood that
Turning next to
In the case of an eclipse, the pixel keeps discharging, while the ADC converts the reset level (SHR). After the reset conversion (SHR), the ADC samples the pixout level again (shown as AE), and compares it, in one clock cycle, to a digital threshold programmed into the ADC's DAC. The digital threshold is set so that some dark current into the pixel is allowed without triggering the comparator.
If the newly sampled reset level (AE) has dropped by more than the DAC's threshold level when compared to the level at which the ADC comparator was reset, eclipse is present and a bit at the output is set.
Next, the TX control is run and the signal level is converted (SHS). When the digital section 550 (
Referring now to
The clamp level can be kept coarse, and unlike a conventional AE clamp, it does not require a large, programmable DAC. Several sensors already have a current clamp which keeps the VLN current per column constant during signal sampling. This current clamp transistor can be re-used by adjusting the gate voltage for the first reset sampling.
The methods shown in
Since there is one more bit of information to be read per pixel, the column memory 546 will increase by one bit cell, typically from 12 bits to 13 bits.
The methods shown in
The methods described herein allow the comparator of the ADC to be reset towards the pixout reset voltage, letting the pixel discharge during the SHR sampling and then the pixout voltage may be compared to a digital threshold. The ADC comparator offset is cancelled and the first reset level becomes a new reference voltage.
Because the ADC checks whether the pixout voltage has drifted more than the digital threshold since the comparator reset, any variation in reference voltage or transistor threshold voltages across the array is cancelled. Furthermore, since the comparator threshold is set digitally in the SAR DAC, it is insensitive to global variations.
Although the invention is illustrated and described herein with reference to specific embodiments, the invention is not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the invention.
This application claims priority of U.S. Provisional Patent Application Ser. 61/468,219, filed Mar. 25, 2011.
| Number | Date | Country | |
|---|---|---|---|
| 61468219 | Mar 2011 | US |
