Patent Application
20210333474
The present invention relates to photonics chips and, more specifically, to structures including an edge coupler and methods of fabricating a structure including an edge coupler.
Photonics chips are used in many applications and systems such as data communication systems and data computation systems. A photonics chip integrates optical components, such as waveguides, optical switches, edge couplers, and polarizers, and electronic components, such as field-effect transistors, into a unified platform. Among other factors, layout area, cost, and operational overhead may be reduced by the integration of both types of components.
An edge coupler is commonly used for coupling laser light between a semiconductor laser and optical components on the photonics chip. The edge coupler may include a narrowed section of a waveguide core that is significantly smaller in cross-sectional than the beam of laser light emitted by the semiconductor laser. Inefficiencies in the coupling between the semiconductor laser and a silicon waveguide core of an edge coupler may occur due to mode size, as well as mode shape. These inefficiencies may lead to significant coupling loss.
Improved structures including an edge coupler and methods of fabricating a structure including an edge coupler are needed.
In an embodiment of the invention, a structure includes an edge coupler having a waveguide core and a shaped layer positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material.
In an embodiment of the invention, a method includes forming an edge coupler having a waveguide core, and forming a shaped layer positioned over a portion of the waveguide core. The waveguide core is comprised of a first material, and the shaped layer is comprised of a second material different in composition from the first material.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
With reference to
The waveguide core 12 may be comprised of a single-crystal semiconductor material, such as single-crystal silicon. In an embodiment, the single-crystal semiconductor material may originate from a device layer of a silicon-on-insulator (SOI) wafer that further includes a buried oxide layer providing the dielectric layer 20 and a substrate 23 comprised of a single-crystal semiconductor material, such as single-crystal silicon. The waveguide core 12 may be patterned from a layer of the single-crystal semiconductor material by lithography and etching processes during front-end-of-line processing of the photonics chip.
The laser 15 may be configured to emit laser light of a given wavelength, intensity, mode shape, and mode size that is directed toward the end surface 16 of the waveguide core 12. The space between the laser 15 and the end surface 16 of the waveguide core 12 may be filled by air or, alternatively, by an index-matching material. The laser 15 may be comprised of III-V compound semiconductor materials. The laser 15 may be, for example, an indium phosphide/indium-gallium-arsenic phosphide laser. The laser 15 may be located on the photonics chip including the waveguide core 12 or, alternatively, may be located off-chip.
The inverse taper 14 may extend lengthwise parallel to the longitudinal axis 17 from the end surface 16 to a transition to the non-tapered section 18. The waveguide core 12 includes opposite sidewalls or side surfaces 22, 24 that increase in separation over a length of the inverse taper 14 with increasing distance from the end surface 16. The side surfaces 22, 24 may be vertical or, alternatively, may be angled with an acute angle relative to the top surface of the dielectric layer 20. The increasing width dimension of the waveguide core 12 over the length of the inverse taper 14 may end at the transition to the non-tapered section 18.
The width dimension of the waveguide core 12 may be measured as a perpendicular distance between the side surfaces 22, 24. The waveguide core 12 may have a width, W1, at the end surface 16, and the waveguide core 12 may have a larger width, W2, at the transition to the non-tapered section 18. The inverse taper 14 may provide the transition in width dimension from the smaller width, W1, to the larger width, W2. In the representative embodiment, the inverse taper 14 of the waveguide core 12 has the width, W1, at the end surface 16 and the inverse taper 14 of the waveguide core 12 has the width, W2, at the transition to the non-tapered section 18. The inverse taper 14 may have a linear width variation for its tapered shape based on a linear function or, alternatively, may have a width that varies based on a non-linear function, such as a quadratic, parabolic, or exponential function, over its length. In a representative embodiment, the width, W1, at the end surface 16 may range from 0.01 times the wavelength of the laser light received from the laser 15 to 0.1 times the wavelength of the laser light received from the laser 15. The inverse taper 14 has a length measured as a distance from the end surface 16 to the transition between the inverse taper 14 and the non-tapered section 18.
In an alternative embodiment, the waveguide core 12 may be comprised of silicon nitride instead of single-crystal silicon. In an alternative embodiment, the substrate 23 may include a groove immediately adjacent to the end surface 16.
With reference to
A shaped layer 28 may be formed on the dielectric layer 26 at a position that is directly over the inverse taper 14 of the waveguide core 12. A portion of the dielectric layer 26 is positioned between the waveguide core 12 and the shaped layer 28. The portion of the dielectric layer 26 prevents direct contact between the waveguide core 12 and the shaped layer 28. The shaped layer 28 is layered in a stack with the inverse taper 14 of the waveguide core 12. The shaped layer 28 is located in a different plane than the waveguide core 12 in order to provide the layered stacking.
The shaped layer 28 may be formed by depositing a layer of a material over the dielectric layer 26 and patterning the deposited layer with lithography and etching processes. To that end, an etch mask is formed by a lithography process over the deposited layer, and unmasked sections of the deposited layer are etched and removed with an etching process, such as reactive ion etching. The shape of the etch mask determines the patterned shape of the shaped layer 28. In the representative embodiment, the shaped layer 28 may have a patterned shape of a block or a slab characterized by an outer perimeter. In the representative embodiment, the patterned shape of the shaped layer 28 may be rectangular with an outer perimeter having corners. The etching process may be selected to stop on the material of the dielectric layer 26 after penetrating fully through the deposited dielectric layer. The shaped layer 28 contains a material having a different composition than the material of the waveguide core 12. In an embodiment, the shaped layer 28 may be comprised of a dielectric material, such as silicon nitride, that is deposited by chemical vapor deposition.
The shaped layer 28 has opposite sidewalls or side surfaces 30, 32 and end surfaces 34, 36 that extend from one side surface 30 to the other side surface 32. The side surfaces 30, 32 and end surfaces 34, 36 of the shaped layer 28 surround the outer perimeter of the shaped layer 28. The end surface 34 may be coplanar or substantially coplanar with (i.e., directly over) the end surface 16 of the waveguide core 12. The end surface 36 may be positioned directly over the transition between the inverse taper 14 and non-tapered section 18 of the underlying waveguide core 12. In the representative embodiment, the shaped layer 28 may be lengthwise positioned over the entirety of the inverse taper 14. In alternative embodiments, the shaped layer 28 may be lengthwise positioned over only a portion of the inverse taper 14. The side surfaces 22, 24 of the inverse taper 14 are arranged between the side surface 30 and the side surface 32 of the shaped layer 28.
The length of the shaped layer 28 may be measured in a direction parallel to the longitudinal axis 17 from the end surface 34 to the end surface 36. The length of the shaped layer 28 may be equal of substantially equal to the length of the inverse taper 14. In alternative embodiments, the length of the shaped layer 28 may be less than the length of the inverse taper 14. The width, W3, of the shaped layer 28 may be measured as a perpendicular distance from the side surface 30 to the side surface 32. The width, W3, of the shaped layer 28 may be greater than the width, W1, of the waveguide core 12 (
With reference to
A back-end-of-line stack 42 is formed over the dielectric layer 40. The back-end-of-line stack 42 includes one or more dielectric layers that may be comprised of dielectric material, such as silicon dioxide, and metallization comprised of, for example, copper or aluminum, that is arranged in the one or more interlayer dielectric layers.
The structure 10, in any of its embodiments described herein, may be integrated into a photonics chip that includes electronic components and additional optical components. For example, the electronic components may include field-effect transistors that are fabricated by CMOS front-end-of-line (FEOL) processing.
The structure 10 provides a monolithically-integrated stacked edge coupler for efficient butt-end light coupling with the laser 15. The structure 10 for the stacked edge coupler is heterogeneous because the materials of the waveguide core 12 and the shaped layer 28 are different in composition. The structure 10 may improve mode matching (i.e., the matching of mode shape and/or mode size) to enhance the efficiency of the light coupling. The shaped layer 28 may be added to the structure without the need for an additional mask in the process flow.
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References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
