Patent Application
20230411927
The optical output of light generating device can be controlled through the use of a driver switch, for example a transistor, that when enabled allows current to flow through the light generating device to emit optical power. Laser diodes are one example of semiconductor light generating devices. Shown in
When the enable signal goes to a logic high, current 120 flows through the driver transistor and the laser as represented by the increase in current at 122. Likewise, at 132, the laser optical power 130 will increase correspondingly. While there can be a delay between when the laser begins consuming electrical power and when the laser begins outputting optical power, that delay will be ignored for purposes of this disclosure.
Disclosed herein are example optical driver circuits having edge rate control. In one aspect of the disclosure, example optical driver circuits include a light generating device, a plurality of drive cells each in a current path of the light generating device, an enable control signal input logically interfaced to each drive cell, where the enable control signal input is adapted to receive an enable control signal, and at least one delay segment logically between at least one of the drive cells and the enable control signal input. In another aspect of the disclosure, each drive cell may include an enable transistor in the current path of a light generating device which is logically interfaced to an enable control signal input. In another aspect of the disclosure, a plurality of drive cells are configured in parallel with respect to each other, such that each drive cell is adapted to pass a fraction of a total current through the light generating device. In yet another aspect of the disclosure, the light generating device is a laser. In one example configuration, at least one of a plurality of drive cells includes a bias control transistor.
Disclosed herein are example optical driver circuits having edge rate control, in which the driver circuits include at least one delay segment and the delay segment is adapted to provide a logic delay of an enable control signal. In another aspect of the disclosure, an input of a logic low to a logic high transition at an enable control signal input of disclosed optical driver circuits results in a step-wise ascending function for a current through a light generating device. In another aspect of the disclosure, a time width of a step within a step-wise ascending function is equal to a time delay associated with at least one delay segment. In yet another aspect of the disclosure, an input of a logic high to a logic low transition at an enable control signal input of disclosed optical driver circuits results in a step-wise descending function for a current through a light generating device. In yet another aspect of the disclosure, at least one delay segment includes at least one of a shift register, a buffer, and/or a timer. In yet another aspect of the disclosure, at least one delay segment has an associated logic time delay and the time delay is configurable.
Disclosed herein are methods of modifying edge rates in an optical driver circuit, the optical driver circuit including a light generating device, a plurality of drive cells each in a current path of the light generating device, an enable control signal input logically interfaced to each drive cell. In one aspect of the disclosure, the methods may include providing an enable control signal to an enable control signal input, communicating the enable control signal to a first drive cell of the plurality of drive cells, delaying the enable control signal to create a delayed enable control signal, and communicating the delayed control signal to a second drive cell of the plurality of drive cells. In another aspect of the disclosure, delaying an enable control signal to create a delayed enable control signal is performed by at least one delay segment. In yet another aspect of the disclosure at least one delay segment includes at least one of a shift register, a buffer, and/or a timer. In another aspect of the disclosure, the methods can include passing a step-wise function for a current through the light generating device.
In one aspect of the disclosure, the enable control signal includes a logic low to a logic high transition and the step-wise function is an ascending step-wise function. In another aspect of the disclosure, the enable control signal includes a logic high to a logic low transition and the step-wise function is a descending step-wise function. In one aspect of the disclosure, the methods may include delaying the delayed control signal to create a further delayed enable control signal and communicating the further delayed control signal to a third drive cell of the plurality of drive cells. In yet another aspect of the disclosure the methods may include delaying the delayed control signal sequentially an integer number “n” times to create further n delayed enable control signals and communicating the further n delayed control signals to a plurality of drive cells, respectively.
While prior art driver designs have utilized an “as fast as possible” design scheme such that the drive current and laser optical power react quickly and fully to changes in an enable drive signal, it may be desirable to have control, for example slowing down, the edge rate of the of the optical drive current/optical power. For example, a sudden jump in current can create large electromagnetic interference (EMI); it may be desirable to control the magnitude of current-generated EMI. Further, optical receivers may desire differing pulse shapes, for example, for various digital signal processing computations, as such a receiver may specify different pulse shapes for receiver input. For purposes of this disclosure, edge rate refers to the rate at which the drive current through the respective optical device, e.g., an increase or decrease laser current, changes in response to a corresponding enable or modulation signal in the driver, which could also be expressed as a slope, an average slope, or derivative of the drive current.
Shown in
Each drive cell 206 may include a driver enable transistor 212a, 212b, 212c . . . 212n, respectively (collectively 212 and using the same numbering scheme for integer n drive cells 206) in the current path of the laser 204. The driver enable transistors 212 each function as an “on”/“off” enable transistor for each drive cell 206 or for time cycling or modulating the laser using an enable control signal 213 at an enable input 214.
Optionally, each drive cell 206 may also, respectively, include bias control transistor 210a, 210b, 210c . . . 210n (collectively 210). The bias control transistors may collectively bias the laser 205 using bias control signal 211 to a desired current level for proper modulation response. An example for deriving the bias control signal using a proxy drive cell is disclosed in U.S. application Ser. No. 17/804,792 title “Current Load-Controlled Laser Driver” and filed on May 31, 2022, which is hereby incorporated by reference herein in its entirety. In such a configuration, the driver enable transistors 212 may be adapted to digitally time cycle the laser 204 via the driver enable gate control signal 213, while the bias control transistors 210, via driver bias gate control signal 211, controls the bias current of the laser 205.
While
In order to slow down the edge rates of the laser 205, as compared to near instantaneous on and off, the driver circuit 200 has a series of delay segments 220 (220a, 220b . . . 220n) logically, respectively, between the enable control signal 213 and one or more of the drive cell 206 enable transistors 212. Each delay segment will establish a pulse delay ΔTa, ΔTb . . . ΔTn, respectively. ΔTa, ΔTb . . . ΔTn can be equivalent time delays or different time delays depending on the configuration. Delay segments 220 can be implemented, for example, through the use of shift registers, CMOS buffer, timers, or other known forms in the art for establishing a pulse delay, e.g. by current starving or restricting each buffer. Further, each individual delay segment 220 can include one or more discrete implementations. For example, a cascade of from 0 to N logic buffers may also be used for each delay segment 220. Further, the delay segments 220 can be programmable, for example a programmable cascade of logic buffers or any other programmable delay circuit. In an alternative configuration, the delay segments 220 could be based on an external timer or clocks, for example using flip-flop circuits, counters, or other implementations using multiples of a set or configurable time base. Other methods of establishing a delay pulse may also be used. See for example U.S. Ser. No. 17/443,110 entitled Pre-Charge Modulation of A Laser Array For 3d Imaging Application and filed Jul. 21, 2021 describes several programmable delay configurations utilizing a multiplexer and is hereby incorporated by reference herein in its entirely.
As shown in
Shown in
The same sequence occurs at time 342 when the enable signal 310 changes from high to low, only the delay now occurs in the edge rate fall of drive current 320 and optical power 330. Accordingly, the drive pulse, i.e., enable signal 213 of
In an alternative configuration, each of the delay segments 220 are configured or programmed to have zero delay in which case all of the drive cells 206 can be turned on simultaneously.
In addition to the advantages discussed above with respect to decreasing the edge rate rise and fall rates, reducing edge rates may also aid in reducing transients and disturbances in power supply and grounds, which could potentially negatively impact other connecting circuits.
