Edge-sensitive dynamic switch

Abstract

An edge-sensitive dynamic switch center around a transmission gate (16) formed with a pair of complementary FET's (Q.sub.N and Q.sub.P) coupled together in parallel between a pair of nodes (1 and 2). The signals at the two nodes vary between a low voltage level and a high voltage level. An inverter (17) is coupled between the gate electrodes of the FET's. A delay element (18) is coupled between one of the nodes and one of the gate electrodes. Due to the transmission delays through the delay element and the inverter, the switch turns off with a controlled delay.

Description

FIELD OF USE

This invention relates to an electronic circuitry employing transmission gates formed with complementary field-effect transistors (FET's).

BACKGROUND ART

A useful building block for a semiconductor integrated circuit (IC) is a transmission gate consisting of a pair of opposite-polarity FET's connected in parallel. Depending on the signals that control the gate, it can be placed in a conductive condition across the full range of the IC power supply voltage. This is highly desirable in many applications.

Referring to FIG. 1, it illustrates how a transmission gate 10 is used in a transition detector as disclosed in U.S. Pat. No. 4,039,858. Gate 10 is composed of an N-channel insulated-gate FET Q0.sub.N and a P-channel insulated-gate FET Q0.sub.P. One source/drain element of FET Q0.sub.N is connected to one source/drain element of FET Q0.sub.P by way of a node 1 at which a gate input signal V.sub.1 is received. The other source/drain element of FET Q0.sub.N is connected to the other source/drain element of FET Q0.sub.P via a node 2 at which a gate output signal V.sub.2 is supplied.

An inverter 11 is connected between the gate electrodes. In response to a signal V.sub.3 provided from a node 3 connected to the Q0.sub.N gate electrode, inverter 11 supplies an inverse signal V.sub.4 to the Q0.sub.P gate electrode.

Signal V.sub.2 is provided to a flip-flop 12 that supplies a signal V.sub.5 representing the flip-flop state. Signal V.sub.2 controls flip-flop 12 when transmission gate 10 is conductive. An EXCLUSIVE NOR gate 13 provides a detection signal V.sub.6 as the EXCLUSIVE NOR of signals V.sub.1 and V.sub.5. The final component of the transition detector is an inverter 14 that generates signal V.sub.3 by inverting signal V.sub.6.

The transition detector operates as follows. Both of FET's Q0.sub.N and Q0.sub.P are normally off so that gate 10 is non-conductive. Signal V.sub.6 is normally at a high voltage. When signal V.sub.1 makes a voltage transition in one direction, the signal transmission delays through the detector enable gate 10 to turn on briefly. This causes a pulse indicative of the transition to appear in signal V.sub.6. A similar pulse occurs in signal V.sub.6 when signal V.sub.1 later makes a transition in the opposite direction.

GENERAL DISCLOSURE OF THE INVENTION

The present invention centers around an electronic circuit in which the transmission delays through circuit components employed with a transmission gate enable the circuit to function as an edge-sensitive dynamic switch with a controlled turn-off delay. The transmission gate is formed with a pair of complementary FET's, each having a first source/drain element, a second source/drain element, and a gate electrode. The first source/drain elements are coupled together through a first node at which a first signal is present. The second source/drain elements are similarly coupled together through a second node at which a second signal is present. An inverter responsive to a third signal at a third node coupled to the gate electrode of one of the FET's provides a substantially inverse fourth signal to the gate electrode of the other FET.

A critical part of the switch is a delay element that causes the third signal to continually follow the first signal, either directly or inversely, by a specified time delay. The delay element is typically an inverting circuit coupled between the first and third nodes. The delay element may, however, be a non-inverting buffer circuit.

The switch turns off in response to a voltage transition of the first signal in one particular direction. By virtue of the transmission delays through the delay element and the (first-mentioned) inverter, one of the FET's turns on briefly when the first signal makes such a transition. This delays the time at which the switch turns off by a controllable amount.

There are a variety of uses for the present switch. It can replace a capacitor in some applications because the delayed turn-off produces a capacitive-like current pulse. For the same reason, the switch can be used in creating dynamic hysteresis. The switch can also be employed to double clock frequencies or make a latch into an edge-sensitive flip-flop.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block/circuit diagram of a prior art transition detector.

FIGS. 2a, 2b, 2c, and 2d are block/circuit diagrams of four general variations of an edge-sensitive dynamic switch in accordance with the invention.

FIGS. 2e and 2f are circuit diagrams for implementations of the main delay element in FIGS. 2a-2d.

FIGS. 3a and 3b are respective timing diagrams for the versions of the dynamic switch shown in FIGS. 2a and 2b.

FIG. 4 is a block/circuit diagram for a portion of a digital IC that employs an input inverting device having dynamic hysteresis.

FIGS. 5a and 5b are timing diagrams pertinent to the digital IC in FIG. 4.

FIG. 6 is a circuit diagram showing how the present switch is employed in a preferred embodiment of the input inverting device of FIG. 4.

Like reference symbols are employed in the drawings and in the description of the preferred embodiments to represent the same or very similar item or items. In the drawings, each N-channel FET has an arrow pointing towards its channel. Each P-channel FET has an arrow pointing away from its channel. All of the FET's shown in the drawings discussed below are enhancement-mode insulated-gate devices.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2a-2d illustrate four general ways for implementing the dynamic switch of the invention. Each of the implementations centers around a transmission gate 16 consisting of complementary FET's Q.sub.N and Q.sub.P connected in parallel between nodes 1 and 2 in the same manner that FET's Q0.sub.N and Q0.sub.P are arranged in the prior art circuit mentioned above. N-channel FET Q.sub.N has a positive threshold voltage V.sub.TN which is typically in the vicinity of 1 volt. P-channel FET Q.sub.P has a negative threshold voltage V.sub.TP that is usually around -1 volt.

Signals V.sub.1 and V.sub.2 are again respectively present at nodes 1 and 2. During normal operation, signal V.sub.1 traverses a voltage range extending from a fixed low supply voltage V.sub.LL to a fixed high supply voltage V.sub.HH. Signal V.sub.2 traverses the same voltage range. Letting V.sub.PS represent the differential power supply voltage V.sub.HH -V.sub.LL, V.sub.PS exceeds both V.sub.TN and .vertline.V.sub.TP .vertline.. For example, V.sub.PS is typically about 5 volts.

An inverter 17 operating in response to signal V.sub.3 supplied from node 3 to the gate electrode of one of FET's Q.sub.N and Q.sub.P provides substantially inverse signal V.sub.4 to the gate electrode of the other FET. Inverter 17 has its input and output respectively connected to the Q.sub.N gate electrode and the Q.sub.P electrode in the embodiments of FIGS. 2a and 2b. The inverter connections are reversed in the implementations of FIGS. 2c and 2d.

A main delay element 18 responsive to signal V.sub.1 generates signal V.sub.3 in such a way that changes in signal V.sub.3 follow changes in signal V.sub.1 either directly or inversely. In FIGS. 2a and 2c, delay element 18 is an inverting circuit whose input and output are respectively connected to nodes 1 and 3. Signal V.sub.3 thus inversely follows signal V.sub.1 in these two versions of the switch. In FIGS. 2b and 2d, element 18 is a non-inverting buffer circuit having its input and output respectively connected to nodes 1 and 3 so that signal V.sub.3 directly follows signal V.sub.1.

Components 17 and 18 are usually implemented in such a manner that signals V.sub.3 and V.sub.4 vary across the entire V.sub.PS voltage range. For example, inverter 17 may be a conventional CMOS-type inverter consisting of a pair of complementary FET's connected in series between supply lines that receive voltages V.sub.LL and V.sub.HH. Element 18 in FIGS. 2a and 2c can be formed in the same way or as an odd number (e.g., 3, 5, . . . ) of such inverters connected in series. FIG. 2e illustrates the case in which element 18 consists of three serially connected CMOS-type inverters 18.sub.1, 18.sub.2, and 18.sub.3. Element 18 in FIGS. 2b and 2d can be implemented as an even number (e.g., 2, 4, . . . ) of conventional CMOS-type inverters connected in series. FIG. 2f shows the case in which element 18 consists of two serially connected CMOS-type inverters 18.sub.4 and 18.sub.5.

The present switch, as represented by the condition of gate 16 and thus by the conditions of FET's Q.sub.N and Q.sub.P, turns off with a controlled time delay in response to a transition of signal V.sub.1 in a particular voltage direction. Referring to FIGS. 3a and 3b, they depict timing diagrams helpful in understanding the operation of the switch. FIG. 3a applies specifically to The implementation of FIG. 2a. FIG 3b applies to FIG. 2b. The voltage curves representing signal V.sub.1 are shown in thicker line in FIGS. 3a and 3b to help distinguish signal V.sub.1 from signals V.sub.3 and V.sub.4.

.tau..sub.A and .tau..sub.B respectively represent the approximate transmission delays through components 18 and 17 measured from threshold to threshold. That is, .tau..sub.A is the difference between the time at which signal V.sub.1 passes the threshold voltage for element 18 and the later time at which signal V.sub.3 passes the same voltage in response to the change in signal V.sub.1. .tau..sub.B is similarly the time period that signal V.sub.4 is delayed relative to signal V.sub.3 measured at the threshold voltage for inverter 17. The total transmission delay from signal V.sub.1 to signal V.sub.4 is .tau..sub.A +.tau..sub.B.

The threshold voltages for components 17 and 18 and, consequently, the transmission delay measurement points are typically about halfway between voltages V.sub.LL and V.sub.HH when components 17 and 18 are implemented using the CMOS-type circuitry described above. This case is shown in FIGS. 3a and 3b.

Turning specifically to FIG. 3a, assume that signal V.sub.1 is initially at low voltage V.sub.LL. V.sub.3 is initially at high voltage V.sub.HH due to the inversion provided by element 18 in FIG. 2a. FET Q.sub.N is turned on since the V.sub.3 -V.sub.1 voltage difference equals power supply voltage V.sub.PS and is therefore greater than N-channel threshold V.sub.TN. Gate 16 is turned on. Signal V.sub.2 is at V.sub.LL. Signal V.sub.4 is also at V.sub.LL. Because signal V.sub.4 is at the same voltage as signals V.sub.1 and V.sub.2, FET Q.sub.P is turned off.

V.sub.1 is now raised to V.sub.HH. V.sub.2 starts following V.sub.1 upward. V.sub.3 -V.sub.1 drops towards -V.sub.PS so as to turn off FET Q.sub.N. Delay .tau..sub.A through element 18 extends the time during which FET Q.sub.N is turned on. This assists V.sub.2 in its upward rise. FET Q.sub.N turns off when V.sub.3 -V.sub.1 drops below V.sub.TN.

V.sub.4 also follows V.sub.1 upward. Due to delays .tau..sub.A and .tau..sub.B through components 18 and 17, there is a short period of time before FET Q.sub.N turns off during which the V.sub.4 -V.sub.1 voltage difference temporarily drops below P-channel threshold V.sub.TP. That is, V.sub.4 trails V.sub.1 by more than .vertline.V.sub.TP .vertline.. This allows FET Q.sub.P to turn on briefly. The dynamic turn on of FET Q.sub.P usually enables V.sub.2 to rise all the way up to V.sub.HH.

FET Q.sub.P turns off when V.sub.4 has risen enough that V.sub.4 -V.sub.1 is greater than V.sub.TP. With FET Q.sub.P now turned off, gate 16 is turned off. The result is that the time at which gate 16 turns off in response to a low-to-high voltage transition in signal V.sub.1 is delayed by an amount dependent on delays .tau..sub.A and .tau..sub.B.

After gate 16 turns off node 2 is effectively disconnected from node 1. The variation in the V.sub.2 voltage, as indicated by the dotted portion of the V.sub.2 curve in FIG. 3a, is now determined by whatever further circuitry is connected to node 2. At a later time, V.sub.1 is returned to V.sub.LL. FET Q.sub.N turns back on to reactivate gate 16. If not already set at V.sub.LL by the further circuitry connected to node 2, V.sub.2 returns to V.sub.LL. This completes the cycle.

The situation is similar with the embodiment shown in FIG. 2b except that the roles of FET's Q.sub.N and Q.sub.P are largely reversed so that the switch has a delayed turn-off when V.sub.1 makes a high-to-low voltage transition. With reference to FIG. 3b, FET Q.sub.P is turned on during the time that V.sub.1 is at V.sub.HH. Gate 16 is conductive. When V.sub.1 is reduced to V.sub.LL, FET Q.sub.N turns on briefly to delay the time at which gate 16 turns off by an amount determined by delays .tau..sub.A and .tau..sub.B.

The implementations of FIGS. 2c and 2d respectively operate in the same way as those of FIGS. 2a and 2b with the voltage polarities and roles of FET's Q.sub.N and Q.sub.P reversed.

When a fast IC interacts with the outside world, the voltages on the internal supply lines often "bounce" up and down. The bounce can cause the IC to operate improperly when it responds to an input signal having a slowly changing voltage. The problem usually becomes more serious as the IC speed increases. FIGS. 4, 5a, 5b, and 6 illustrate an example of how the present dynamic switch is employed in creating dynamic hysteresis to prevent supply line bounce from causing improper IC operation.

Beginning with FIG. 4, it shows a portion of a digital IC 20 that receives supply voltages V.sub.HH and V.sub.LL at respective supply terminals (or pads) T.sub.H and T.sub.L. IC 20 produces a circuit output voltage V.sub.O at an output terminal T.sub.O in response to a circuit input voltage V.sub.I received at an input terminal T.sub.I. A capacitor C.sub.O (real or parasitic) is connected between terminal T.sub.O and the V.sub.LL supply.

The illustrated portion of IC 20 is a very fast logic circuit powered by high and low internal supply voltages V.sub.H and V.sub.L provided on lines connected respectively to terminals T.sub.H and T.sub.L. Responsive to an internal input voltage V.sub.A supplied on a line connected to terminal T.sub.I, the logic circuit produces an internal output voltage V.sub.D on a line connected to terminal T.sub.O. Parasitic inductances L.sub.L, L.sub.H, L.sub.I, and L.sub.O are respectively associated with the lines carrying voltages V.sub.L, V.sub.H, V.sub.A, V.sub.D.

The logic circuit consists of (a) an input inverting device 22 formed with an input inverter 23 and a dynamic hysteresis circuit 24 that together generate a voltage V.sub.B inverse to voltage V.sub.A, (b) an intermediate logic section 26 that operates on voltage V.sub.B and possibly on other input voltages (not shown) to produce a voltage V.sub.C at a value that is logically the same as or inverse to voltage V.sub.B, and (c) an output inverter 27 that generates voltage V.sub.D as the inverse of voltage V.sub.C. Inverter 23 is a conventional CMOS-type inverter formed with complementary input FET's Q1.sub.N and Q1.sub.P. Inverter 27 is similarly formed with complementry output FET's Q2.sub.N and Q2.sub.P.

Dynamic hysteresis circuit 24 consists of a control circuit 28 powered by supply voltages V.sub.H and V.sub.L, an N-channel FET Q3.sub.N, and a P-channel FET Q3.sub.P. In response to voltage V.sub.B control circuit 28 supplies threshold-control voltages V.sub.N and V.sub.P to the respective gates of FET's Q3.sub.N and Q3.sub.P. FET Q3.sub.N is "in parallel" with FET Q1.sub.N. FET Q3.sub.P is similarly in parallel with FET Q1.sub.P.

Circuit 24 provides dynamic hysteresis for the threshold voltage V.sub.T of device 22. More particularly, the threshold voltage for an inverter formed with complementary FET's depends on the ratio R.sub.P/N of the P-channel width to the N-channel width (at constant channel length). This means the widths of the channel areas that are conducting at the threshold point. The threshold voltage increases when R.sub.P/N increases and vice versa.

FET's Q3.sub.N and Q3.sub.P are normally off or at so low conductive levels as to be effectively off. Accordingly, the quiescent value of R.sub.P/N for device 22 is simply the Q1.sub.P channel width divided by the Q1.sub.N channel width since FET's Q1.sub.N and Q1.sub.P are both conducting at the threshold point, one in the midst of turning on and the other in the midst of turning off. If FET Q3.sub.N is on but FET Q3.sub.P is off, the N-channel width for device 22 increases since FET's Q3.sub.N and Q1.sub.N are in parallel. R.sub.P/N for device 22 is therefore less than its quiescent value. In like manner, R.sub.P/N for device 22 is greater than the quiescent value when FET Q3.sub.P is on but FET Q3.sub.N is off.

With the foregoing in mind, device 22 operates as follows. FET's Q3.sub.N and Q3.sub.P are initially off. Supply voltages V.sub.L and V.sub.H are initially at (or very near) respective substantially constant levels V.sub.LL and V.sub.HH. Under these conditions, threshold V.sub.T is at a quiescent value V.sub.S determined by the quiescent R.sub.P/N of device 22. When the difference V.sub.A -V.sub.L passes V.sub.T, device 22 changes state.

If V.sub.A rises above V.sub.LL +V.sub.S, FET Q1.sub.N turns on and FET Q1.sub.P turns off. Device 22 as represented by the conductive conditions of FET's Q1.sub.N and Q1.sub.P switches from a high logic state to a low logic state, causing V.sub.B to go from a high level near V.sub.HH to a low level near V.sub.LL. Responsive to this change in V.sub.B, control circuit 28 temporarily raises V.sub.N enough to turn FET Q3.sub.N on for a brief period. FET Q3.sub.P remains off. R.sub.P/N drops below its quiescent level. This reduces V.sub.T until circuit 28 reduces V.sub.N sufficiently to turn FET Q3.sub.N back off.

Largely the reverse occurs when V.sub.A drops below V.sub.LL +V.sub.S. FET Q1.sub.N turns off and FET Q1.sub.P turns on, causing device 22 to switch from its low logic state to its high logic state. V.sub.B goes from V.sub.LL up to V.sub.HH. In response to this V.sub.B change, circuit 28 temporarily provides V.sub.P at a sufficiently low voltage to turn FET Q3.sub.P on for a short time. FET Q3.sub.N stays off. Consequently, R.sub.P/N rises above its quiescent value so as to increase V.sub.T. When circuit 28 subsequently raises V.sub.P to turn off FET Q3.sub.P, V.sub.T drops back down.

Now, look at what happens in IC 20 if input V.sub.I changes very slowly. Assume (for example) that logic section 26 provides a voltage inversion so that V.sub.C is the inverse of V.sub.B.

First consider how IC 20 would operate if (as in the prior art) dynamic hysteresis circuit 24 were absent. This case is represented by the voltage variations shown in FIG. 5a. Assume that V.sub.I is initially low. Also assume that V.sub.L and V.sub.H are respectively at V.sub.LL and V.sub.HH. V.sub.A is then low, causing V.sub.B to be at V.sub.HH. V.sub.C is low so that FET Q2.sub.N is turned off and FET Q2.sub.P is turned on. V.sub.D and V.sub.O are both at V.sub.HH. Capacitor C.sub.O is charged to a high level.

As V.sub.I rises slowly, V.sub.A tracks V.sub.I closely. Inductance L.sub.I does not have any significant effect. At a time t.sub.1, V.sub.A starts to go above V.sub.LL +V.sub.S. This causes V.sub.B to drop rapidly to V.sub.LL. V.sub.C goes high to turn FET Q2.sub.N on and FET Q2.sub.P off. V.sub.D drops rapidly to V.sub.LL. At a time t.sub.2 depending on the transmission delays through components 26 and 27, capacitor C.sub.O starts discharging to the V.sub.LL supply by way of a path through elements L.sub.O, Q2.sub.N, and L.sub.L to pull V.sub.O rapidly down to V.sub.LL.

The current flowing through this path varies with time in a non-linear manner. Since the voltage across an inductor is the inductance times the time rate of change of current flowing through the inductor, a positive voltage builds up across inductance L.sub.L, reaching a maximum at a time t.sub.3. A positive (or upward going) spike in V.sub.L thereby occurs at t.sub.3 as shown in FIG. 5a. The V.sub.L spike at t.sub.3 is the "first" spike in a set of timewise contiguous pairs of alternating apikes that die out quickly, of which only the first pair of alternating spikes are actually shown in FIG. 5a.

The V.sub.L spike at t.sub.3 is often so high that V.sub.A -V.sub.L temporarily drops below threshold V.sub.T. See shaded area 29 in FIG. 5a. Inverter 23 then makes a pair of rapid changes in logic state at approximately a time t.sub.4, causing V.sub.B to spike upwards. In turn, the V.sub.B spike causes a positive V.sub.O spike to occur at a time t.sub.5.

The same situation arises if V.sub.I drops slowly, except that the polarities and supply lines are reversed. The first spike is a negative V.sub.H spike that results from the rapid charging of capacitor C.sub.O by way of a path through elements L.sub.H, Q2.sub.P, and L.sub.O.

The V.sub.O spikes and the corresponding spikes in V.sub.B, V.sub.C, and V.sub.D can be disastrous. They could cause a circuit (such as a flip-flop) responsive to V.sub.O, V.sub.B, V.sub.C, or V.sub.D to be set at a wrong state.

Circuit 24 enables IC 20 to avoid unwanted changes of state that would otherwise occur as a result of supply line bounce. FIG. 5b, which is an analogous timing diagram to FIG. 5a for the case in which circuit 24 is present, is helpful in showing how this is accomplished.

The initial conditions for the case shown in FIG. 5b are the same as those for FIG. 5a. As V.sub.I rises slowly, V.sub.A follows closely. When V.sub.A passes V.sub.LL +V.sub.S at time t.sub.1, V.sub.B drops rapidly to V.sub.LL. In response, hysteresis circuit 24 reduces V.sub.T starting at a time t.sub.1.5. The difference between dotted line 30 and the solid line representing V.sub.A -V.sub.T in FIG. 5b indicates the amount of reduction in V.sub.T.

Capacitor C.sub.O starts discharging at time t.sub.2. This produces a positive V.sub.L spike at time t.sub.3 according to the mechanism described above. Due to the V.sub.T reduction produced by circuit 24, V.sub.A -V.sub.L stays above V.sub.T during the positive V.sub.L spike. Capacitor C.sub.O thereby remains discharged so as to substantially inhibit any further internal supply line voltage bounce. Accordingly, no spikes occur in V.sub.B, V.sub.C, V.sub.D, and V.sub.O. At a later time t.sub.3.5, V.sub.T automatically returns to V.sub.S.

The situation in which V.sub.I falls slowly is essentially the complement of that shown in FIG. 5b. In the interval between t.sub.1.5 and t.sub.3.5, circuit 24 increases V.sub.T by an amount sufficient to prevent spikes from occurring in V.sub.B, V.sub.C, V.sub.D, and V.sub.O. If section 26 supplies V.sub.C at the same logical value as V.sub.B, circuit 24 operates in basically the same way to prevent undesired changes in state.

The dynamic switch of the invention is employed in a capacitive-like mode in a preferred embodiment of control circuit 28 shown in FIG. 6. Circuit 28 consists of (a) an inverter 34 formed with complementary FET's Q4.sub.N and Q4.sub.P that produce a voltage V.sub.E inverse to voltage V.sub.B, (b) dynamic switches 35.sub.N and 35.sub.P that respectively produce voltages V.sub.N and V.sub.P in response to voltage V.sub.E, and (c) complementary discharge FET's Q5.sub.N and Q5.sub.P whose gate electrodes receive a voltage V.sub.G. FET Q5.sub.N is source-drain connected between the V.sub.L line and the Q3.sub.N gate. FET Q5.sub.P is source-drain connected between the V.sub.H line and the Q3.sub.P gate.

Switch 35.sub.N consists of an inverter 36 that provides a voltage V.sub.F as the inverse of voltage V.sub.E, an inverter 38 that produces voltage V.sub.G as the inverse of voltage V.sub.F, and a transmission gate 40. Inverter 36 is formed with complementary FET's Q6.sub.N and Q6.sub.P. Inverter 38 is formed with complementary FET's Q7.sub.N and Q7.sub.P. Transmission gate 40 is formed with complementary FET's Q8.sub.N and Q8.sub.P whose gate electrodes respectively receive voltages V.sub.F and V.sub.G. FET's Q8.sub.N and Q8.sub.P have interconnected first source/drain elements connected to the Q4.sub.N and Q4.sub.P drains and interconnected second source/drain elements connected to the Q3.sub.N gate. Consequently, switch 35.sub.N is an embodiment of the switch version shown in FIG. 2a.

Switch 35.sub.P consists of a transmission gate 42 along with inverters 36 and 38. Gate 42 consists of complementary FET's Q9.sub.N and Q9.sub.P arranged with regard to the Q3.sub.P gate in a manner that is complementary to the arrangement of gate 40 with respect to the Q3.sub.N gate. Switch 35.sub.P is thus an embodiment of the version shown in FIG. 2c.

Circuit 28 in FIG. 6 operates as follows. Assume that V.sub.B is initially at V.sub.HH so that FET Q4.sub.N is on and FET Q4.sub.P is off. V.sub.F is likewise at V.sub.HH. V.sub.E and V.sub.G are both at V.sub.LL. FET Q8.sub.N is on, thereby setting V.sub.N at V.sub.LL. FET's Q3.sub.N, Q5.sub.N, and Q8.sub.N are all off.

When V.sub.B drops to V.sub.LL, FET Q4.sub.N turns off and FET Q4.sub.P turns on. V.sub.E starts rising toward V.sub.HH. During an initial part of the time needed for inverter 36 to drop V.sub.F down to V.sub.LL, positive charge from the V.sub.H line flows through FET's Q4.sub.P and Q8.sub.N to the Q3.sub.N gate. V.sub.N starts to rise as FET Q8.sub.P turns on. Although FET Q8.sub.N gradually turns off, positive charge from the V.sub.H line now flows through FET's Q4.sub.P and Q8.sub.P to the Q3.sub.N gate to raise V.sub.N further. This continues for the entire time needed for inverter 36 to raise V.sub.G up to V.sub.HH. At some point during the charging of the Q3.sub.N gate, FET Q3.sub.N turns on.

When inverter 38 finally switches, FET Q8.sub.P turns off to stop the charging of the Q3.sub.N gate. At this point, FET Q5.sub.N turns on. It opens a path to the V.sub.L line for discharging the Q3.sub.N gate, causing FET Q3.sub.N to turn off. Inverters 36 and 38 and FET's Q4.sub.N, Q9.sub.N, Q9.sub.P, and Q5.sub.P operate in a similar, complementary manner to enable FET Q3.sub.P to turn on briefly when V.sub.B later returns to V.sub.HH.

If the transmission delay of inverter 36 or 38 is too small to allow enough time to charge the Q3.sub.N gate and/or the Q3.sub.P gate, a further delay element can be placed in series with inverter 36 or 38. The delay element might, for example, consist of a pair of inverters in series.

While the invention has been described with reference to particular embodiments, this description is solely for the purpose of illustration and is not to be construed as limiting the scope of the invention claimed below. For example, junction FET's could be used instead of insulated-gate FET's. Certain of the enhancement-mode FET's could be replaced with depletion-mode FET's. Various modifications and applications may thus be made by those skilled in the art without departing from the true scope and spirit of the invention as defined by the appended claims.

Claims

1. An electronic circuit comprising (a) a pair of complementary field-effect transistors (FET's), each having a first source/drain element, a second source/drain element, and a gate electrode, the first source/drain elements coupled together through a first node at which a first signal is present, the second source/drain elements coupled together through a second node at which a second signal is present, both of the first and second signals substantially varying between a low voltage level and a high voltage level, and (b) an inverter responsive to a third signal at a third node coupled to the gate electrode of one of the FET's for providing a substantially inverse fourth signal to the gate electrode of the other FET, characterized by delay means for causing the third signal to continually follow the first signal, either directly or inversely, by a specified time delay.

2. A circuit as in claim 1 characterized in that the inverter provides a further time delay such that the fourth signal continually follows the first signal, either inversely or directly, by the sum of the two delays.

3. A circuit as in claim 1 characterized in that the delay means comprises inverting means coupled between the first and third nodes.

4. A circuit as in claim 3 characterized in that the inverting means comprises a single inverter or an odd number of inverters coupled in series.

5. A circuit as in claim 3 characterized in that the FET's are enhancement-mode insulated-gate FET's.

6. A circuit as in claim 1 characterized in that delay means comprises non-inverting buffer means coupled between the first and third nodes.

7. A circuit as in claim 6 characterized in that the buffer means comprises an even number of inverters coupled in series.

8. A circuit as in claim 6 characterized in that the FET's are enhancement-mode insulated-gate FET's.

9. A circuit as in claim 1 further including circuit means coupled to the second node for producing a further signal that varies in response to the second signal as it varies between the low and high voltage levels.

10. A circuit as in claim 9 wherein the circuit means comprises logic means for performing a logical operation.

11. A circuit as in claim 10 characterized in that the inverter provides a further time delay such that the fourth signal continually follows the first signal, either inversely or directly, by the sum of the two delays.