Claims
- 1. A semiconductor memory cell comprising:
- a first oxide layer formed on a semiconductor substrate;
- a first implant region of a tunneling gate in said substrate defined beneath said first oxide layer;
- a first dose of a conductive material implanted within said first implant region;
- a second implant region of said tunneling gate formed adjacent said first implant region in said substrate, within a tunnel area of said first oxide layer;
- a second dose, different from said first dose, of a conductive material implanted within said second implant region such that said second dose does not substantially overlap said first dose; and
- a tunnel window oxide layer grown over said second dose in said tunnel area on said substrate.
- 2. Semiconductor memory cell according to claim 1, wherein said cell is a E.sup.2 PROM cell having a floating gate and a tunneling gate.
- 3. A semiconductor memory cell for use in an E.sup.2 PROM comprising:
- a substrate;
- a floating gate for storing a charge; and
- a coupling gate and a tunneling gate for charging and discharging said floating gate, said tunneling gate being formed within said substrate and including a conductive first implant region having a first dose of a first implant material and a second conductive implant region having a second dose, different from said first dose, of a second implant material adjacent said first implant region, wherein said first and second implant materials do not substantially overlap.
- 4. Semiconductor memory cell according to claim 3, wherein said first implant region and said second implant region are formed with the same implant material.
- 5. Semiconductor memory cell according to claim 4, wherein said first implant material is arsenic and said second implant material is phosphorous.
- 6. Semiconductor memory cell according to claim 3, wherein said first implant region is formed with a first dose of conductive material and said second implant region is formed with a second dose of conductive material.
- 7. A device according to claim 1, further including:
- a second oxide layer formed on said first oxide layer over said first implant in said first region, said second implant region being formed within a tunnel area of said first and second oxide layers.
Parent Case Info
This application is a continuation of application Ser. No. 07/992,778, filed Dec. 18, 1992, now abandoned, which is a divisional of application Ser. No. 07/758,554 filed Sep. 12, 1991 now U.S. Pat. No. 5,198,381.
US Referenced Citations (7)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0060408 |
Sep 1982 |
EPX |
4105636 |
Aug 1991 |
DEX |
2085226 |
Apr 1982 |
GBX |
Non-Patent Literature Citations (3)
Entry |
"Comparison And Trends In Today's Dominant E.sup.2 Technologies", by S. K. Lai et al, IEEE, dated 1986, pp. 580-583. |
International Search Report dated Dec. 28, 1992. |
"A Million Cycle CMOS 256K Bit EPROM", IEEE Journal of Solid State Circuits, by D. Cioaco et al, vol. SC-22, No. 5, Oct. 1987, pp. 684-692. |
Divisions (1)
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Number |
Date |
Country |
Parent |
758554 |
Sep 1991 |
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Continuations (1)
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Number |
Date |
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992778 |
Dec 1992 |
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