This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2009-0127357, filed on Dec. 18, 2009, and Korean Patent Application No. 10-2010-0097527, filed on May 20, 2010, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a wire/wireless communication system, and more particularly, to, among methods that belong to a channel coding technology field, an encoding method generating a low density parity-check (LDPC) code.
2. Description of the Related Art
In a wire/wireless communication system, a signal transmitted in a digital form may not be demodulated at a receiver depending on a channel condition. Among various techniques which are adopted in order to reduce error occurrence rate which is increased due to high-speed communication, a channel coding technique is representatively adopted. In recent years, the channel coding technique has been applied to almost all wireless communication systems. In particular, an LDPC code is becoming a focus as a next-generation channel codec in the wireless communication system. First, it is assumed that the LDPC code is encoded by a systematic method. That is, a part of a packet is configured in the same form as inputted bits and the rest part of the packet is configured by a parity bit acquired through the inputted bits. Accordingly, only when input signals are inputted into all blocks that take charge of an encoding function, an encoding operation is performed. A ratio at which the parity bit corresponds to the entire packet depends on encoding rate. Accordingly, the encoding rate is fixed by a parity-check matrix.
The LDPC code is designed by Gallager. The LDPC code is defined by the parity-check matrix of which a small minority of elements have a value of 1 and the rest of most elements have a value of 0.
The LDPC code is divided into a regular LDPC code and an irregular LDPC code. In the case of the regular LDPC code, all rows in the parity-check matrix have the same number of is as elements and all columns also have the same number of is as elements. Contrary to this, in the parity-check matrix of the irregular LDPC code, rows including different numbers of 1s are provided or columns including different numbers of 1s are provided. In general, it has been known that error correction performance of the irregular LDPC code is more excellent than that of the regular LDPC code.
Meanwhile, Fossorier has proposed a quasi-cyclic LDPC code (“Quasi-Cyclic Low Density Parity Check Codes from Circulant Permutation Matrices”, EEE Trans. Inform. Theory, vol. 50, pp. 1788-1794, August 2004) representing the elements of the parity-check matrix by a cyclically shifted identity matrix and a matrix of 0, not 0 and 1 which are elements on GF(2). The LDPC code adopted in IEEE 802.16e or 802.11n is an irregular type quasi-cyclic LDPC code and a parity bit part has a block-type dual-diagonal matrix form.
As the prior art, Richardson (“Efficient Encoding of Low-Density Parity-Check Codes”, IEEE Transactions on Information Theory, Vol. 47, No. 2, February 2001) has proposed a method of generating parity bits by simultaneous equations of input vectors and sub-matrices by blocking and dividing the parity-check matrix of the LDPC code, generating parity bits through relevant matrix equations, and subdividing the parity-check matrices into six sub-matrices.
Contrary to this, Zongwang Li, etc., (“Efficient Encoding of Quasi-Cyclic Low-Density Parity-Check Codes”, IEEE Transactions on Communications, Vol. 54, No. 2, January 2006) has proposed a technique of generating parity bits through an encoding apparatus that divides a matrix multiplication operation of a generation matrix acquired by using the parity-check matrix of the QC-LDPC code and information bits into two sequential steps and implements each step as a cyclic shift-register.
In the prior art, complexity of hardware is increased in implementation and the number of all clocks consumed is increased while performing continuous encoding.
There is an object of the present invention to perform high-speed LDPC encoding through low additional complexity by preventing complexity generated by a non-linear operation and directly using a parity-check matrix proposed in a standard.
There is another object of the present invention to provide an effective high-speed LDPC encoding apparatus through low additional linear complexity by using a parity-check matrix proposed in an IEEE 802.1x standard instead of an arbitrary parity-check matrix of the LDPC code in implementing an LDPC encoding apparatus.
The objects of the present invention are not limited to the above-mentioned objects and other undescribed objects will be apparently appreciated by those skilled in the art from the following descriptions.
In order to achieve the above-mentioned objects, an LDPC encoding method according an aspect of the present invention includes performing LDPC encoding by a unique method different from a known encoding method by using a parity-check matrix proposed in an IEEE 802.1x standard instead of an arbitrary parity-check matrix of an LDPC code.
The LDPC encoding method may include performing entire encoding through successive execution of partial encoding operations by applying a quasi-cyclic characteristic of the parity-check matrix to the encoding method.
In particular, the LDPC encoding method according to the aspect of the present invention maximally reduces the number of cyclic shift-registers under an idle state. In addition, the LDPC encoding method according to the aspect of the present invention performs high-speed encoding by partially starting encoding of individual information vectors while partitioning each of square matrices constituting the parity-check matrix proposed in the standard per row at a regular interval.
In order to achieve the above-mentioned objects, an LDPC encoding apparatus according to another aspect of the present invention includes: an arbitrary parity bit generation block generating an arbitrary parity bit; a temporary parity bit generation block generating a temporary parity bit corresponding to the arbitrary parity bit every clock by receiving the arbitrary parity bit and an information vector; a correction bit generation block generating a correction bit corresponding to the arbitrary parity bit every clock by receiving the arbitrary parity bit and the temporary parity bit; and a parity bit correction block generating a corrected parity bit every clock by receiving the arbitrary parity bit, the temporary parity bit, and the correction bit.
According to an embodiment of the present invention, by applying an effective high-speed LDPC encoding apparatus to a wire/wireless communication system, linear complexity is generated by an encoding method directly using a parity-check matrix in implementing the encoding apparatus, thereby reducing complexity of hardware in comparison with known methods.
Continuous encoding of a plurality of information vectors has an advantage of implementing a more effective encoding apparatus by decreasing the number of all clocks consumed for continuous encoding through efficiently using a register of an encoding apparatus.
Further, it is possible to increase the speed of the encoding apparatus through a method of dividing a circulant permutation matrix at regular intervals per row with low additional complexity as necessary.
Advantages and characteristics of the present invention, and methods for achieving them will be apparent with reference to embodiments described below in detail in addition to the accompanying drawings. However, the present invention is not limited to the exemplary embodiments to be described below but may be implemented in various forms. Therefore, the exemplary embodiments are provided to enable those skilled in the art to thoroughly understand the teaching of the present invention and to completely inform the scope of the present invention and the exemplary embodiment is just defined by the scope of the appended claims. Meanwhile, terms used in the specification are used to explain the embodiments and not to limit the present invention. In the specification, a singular type may also be used as a plural type unless stated specifically.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. First of all, we should note that in giving reference numerals to elements of each drawing, like reference numerals refer to like elements even though like elements are shown in different drawings. Further, in describing the present invention, well-known functions or constructions will not be described in detail since they may unnecessarily obscure the understanding of the present invention.
Prior to describing the present invention, a related writing method of the QC-LDPC code and a parity-check matrix H proposed in the IEEE 802.11n and 802.16e standards will be described. A circulant permutation matrix is defined as a square matrix in which rows have the same weight and a top row to a bottom row are cyclically disposed. Further, the first row of the circulant permutation matrix is defined as a generator of the circulant permutation matrix. The circulant permutation matrix is completely generatable through the generator and is represented by the generator. As one example, a circulant permutation matrix of which the rows have a weight of 1 may be defined. Specifically, a matrix A=(Ai,j) is defined as a B×B permutation matrix defined by Equations 1 and 2.
A matrix Ai is defined as a circulant permutation matrix in which a B×B identity matrix is shifted right by i with respect to i which is in the range of integers 0 to B−1. A B×B zero matrix is defined as A−. Accordingly, i has a sample space of {−, 0, 1, . . . , B−1} and Ai has a sample space of {A−, A0, A1, . . . , AB-1}. u is defined as an information vector having a form of u=(ui,0, ui,1, . . . , ui,B-1) with respect to (u0, u1, . . . , uK-1) and i which is in the range of integers 0 to K−1. u is encoded as a codeword c having a form of (cs|cp). cs has a form of (u0, ui, . . . , uK-1) and is defined as a vector of 1×(KB) corresponding to a systematic part of c, and cp has a form of pi=(pi,0, pi,1, . . . , pi,B-1) with respect to (p0, p1, . . . , pM-1) and i which is in the range of integers 0 to M−1 and is defined as a vector of 1×(MB) corresponding to a parity part of c. All ui,j and pi,j are defined in GF(2). ⊕ is defined as the addition defined in GF(2).
H is (MB)×(NB) matrix and is defined as:
and all si,j are defined in the sample space {−, 0, 1, . . . , B−1}. As described above, an LDPC code encoded by using H constituted by the circulant permutation matrices is defined as a QC-LDPC code. Hs is defined as the (MB)×(KB) matrix related with the systematic part of c. Hp is defined as the (MB)×(MB) matrix related with the parity part of c. P(H) is defined as a circular matrix of H in which each of a zero matrix and a circulant permutation matrix of H is written as 0 and 1. E(H) is defined as an index matrix of H. E(Hs) and E(Hp) are also defined in the same manner as E(H). E(H), E(Hs), and E(Hp) are defined as:
H proposed in the IEEE 802.11n and 802.16e standards is constituted by the systematic part and the parity part. The systematic part has the circulant permutation matrix form and the parity part has a dual-diagonal parity structure. The dual-diagonal parity structure is defined in a form of
si,j=−elsewhere. As one example, E (Hp) at M=6 may be written as
A parity-check matrix having ½ code rate and a codeword length of 1944 bits proposed in an actual IEEE 802.11n standard is shown in
Referring to
Referring to
Specifically, the LDPC encoding apparatus 100 according to the embodiment of the present invention is constituted by an arbitrary parity bit generation block 110, a temporary parity bit generation block 120, a correction bit generation block 130, and a parity bit correction block 140.
The arbitrary parity bit generation block 110 generates an arbitrary parity bit P0 used in the temporary parity bit generation block 120, the correction bit generation block 130, and the parity bit correction block 140.
Referring to
Equation 3 represents an operation in the temporary parity bit generation block 120. In the following equation, ai,j is defined as a generator of As
An operation of the temporary parity bit generation block 120 will be described in detail below.
Prior to starting encoding, the information vector u is transferred to the cyclic left shift-registers 210 in advance. The cyclic left shift-registers 210 are connected to M adders 220 through global wires. Since the encoding apparatus using H is extended from the encoding apparatus using P(H), the number of global wires required is not increased but maintained as it is. In spite of the extension from P(H) to H, the present invention is characterized in that complexity is not increased.
In order to perform encoding based on the dual-diagonal parity-check matrix proposed in the standards, the arbitrary parity bit generation block 110 arbitrarily generates a parity bit P0, first of all. For example, the arbitrary parity bit P0 may be set as a zero vector of 1×B for a simple operation.
Next, the temporary parity bit generation block 120 partially generates other temporary parity bits Pi based on the arbitrary parity bit P0 every clock with respect to i which is in the range of integers 1 to M−1 for successive (M−2)+B clocks. When the clock is (M−2)+(B−1), other temporary parity bits Pi with respect to i which is in the range of integers 1 to M−1 are completely generated.
The correction bit generation block 130 generates a correction bit p0c with respect to the arbitrary parity bit P0. P0c is also partially generated every clock for successive B clocks. When the clock is (M−1)+(B−1), p0c is completely generated. An equation of the correction bit generation block 130 based on the block is expressed as shown in Equation 4.
Generation of modified bit P0c{(M−1)≦t≦(M−1)+B}:
P
0,t-(M-1)
c
=P
0,(t-(M-1))⊕,(s
)
⊕P
M-1,t-(M-1)
⊕X
M-1,t-(M-1) [Equation 4]
The parity bit correction block 140 partially corrects the arbitrary parity bit P0 and other temporary parity bit Pi with respect to i which is in the range of integers 1 to M−1 every clock in the parity part of the parity-check matrix for the successive B clocks as shown in Equation 5 below. As a result, the LDPC encoding apparatus 100 according to the embodiment of the present invention successively performs M parallel part encoding.
Hereinafter, characteristics of the present invention will be described in comparison with a 2-step encoding method in the prior art developed by Zongwang Li, etc.
First, according to the 2-step encoding method, when clocks consumed for the information vector u inputted into the temporary parity bit generation block 120 are disregarded, M+s0,K+B clocks are consumed to encode KB information bits.
However, according to the embodiment of the present invention, in the case of successively encoding n information vectors u, (M+s0,K+B)+(n−1)×(s0,K+B) clocks less than n×(M+s0,K+B) clocks are consumed.
Second, when the information vector u is encoded by using the encoding method of the embodiment of the present invention, sub-blocks and blocks that are under an idle state exist after a B−1 clock, referring to
On the contrary, in the 2-step encoding method, until encoding a former information vector u is completed, encoding a subsequent information vector u cannot be performed. When the 2-step encoding method is used at the time of performing successive encoding with respect to n information vectors u, n×(2B) clocks more than the encoding method according to the embodiment of the present invention are consumed.
Third, in terms of using the cyclic left shift-register 210, an operation of the sub-block of each of the cyclic left shift-register 210 and the adder 220 according to the embodiment of the present invention is similar to the first step of the 2-step encoding method. However, the cyclic left shift-register 210 used in the embodiment of the present invention is induced by the extension from the encoding apparatus using P(H) to the encoding apparatus using H and the cyclic left shift-register 210 used in the 2-step encoding method is induced while encoding is performed by applying matrix decomposition to a generation matrix G acquired through H.
Accordingly, the number of global wires connected to the cyclic left shift-register 210 of the LDPC encoding apparatus 100 according to the embodiment of the present invention is equal to the number of global wires connected to the cyclic left shift-register at the first step of the 2-step encoding method.
However, in the case of the 2-step encoding method, the cyclic left shift-register at the second step additionally requires global wires more than the global wires at the first step due to an inverse matrix operation of Hp at the second step.
For accurate appreciation of the present invention, hereinafter, an encoding apparatus implemented by using an actual circular matrix P(H) and a parity-check matrix extending P(H) will be described with reference to
Examples of E(H) and E(Gp) of E(H) for helping appreciation of the present invention are as follows and a matrix Gp is defined as a matrix corresponding to the parity part of the systematic G. E(Gp) is defined by circulant index forms which is the sum of the circulant permutation matrices. As one example, a circulant having an index of 0⋄1⋄4 is defined by the sum of circulant permutation matrices A0, A1, and A4.
Referring to
Referring to
Specifically, an operation clock of each sub-block 230 in the temporary parity bit generation block 120 is changed from the successive B clocks to B+s0,K clocks and an operation clock of the correction bit generation block 130 is changed from the successive B clocks to B+s0,K clocks to implement the extended LDPC encoding apparatus 100. Further, in terms of substantially implementing the LDPC encoding apparatus 100, an adder of P3,i with respect to i which is in the range of integers 0 to 3 and gray registers are used. On the basis of the encoding apparatus using P(H), the extended LDPC encoding apparatus 100 according to the embodiment of the present invention requires additional s0,K gray register column vectors in accordance with s0,K.
Referring to
Referring to
Referring to
Next, the temporary parity bit generation block 120 adds and converts received information vectors and partially generates a temporary parity bit in sequence every clock by using the converted vector X and the arbitrary parity bit (S120). For example, the temporary parity bit generation block 120 partially generates other temporary parity bits Pi based on the arbitrary parity bit P0 every clock with respect to i which is in the range of integers 1 to M−1 for successive (M−2)+B clocks by using Equation 1. When the clock is (M−2)+(B−1), other temporary parity bits Pi with respect to i which is in the range of integers 1 to M−1 are completely generated.
Next, the correction bit generation block 130 generates a correction bit P0c with respect to the arbitrary parity bit P0 (S130). P0c is also partially generated every clock for successive B clocks. When the clock is (M−1)+(B−1), P0c is completely generated. An equation of the correction bit generation block 130 based on the clock is expressed as shown in Equation 2.
The parity bit correction block 140 partially corrects the arbitrary parity bit P0 and other temporary parity bit Pi with respect to i which is in the range of integers 1 to M−1 every clock for the successive B clocks as shown in Equation 3 (S140). As a result, the LDPC encoding apparatus 100 according to the embodiment of the present invention successively performs M parallel part encoding.
In the encoding apparatus according to another embodiment of the present invention, partitioning each of square matrices constituting the parity-check matrix per row at a regular interval enables the encoding operation so as to perform high-speed encoding. Herein, the encoding speed of the information vector u depends on the size of the square matrix and a row-unit partitioning interval of the square matrix.
While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the embodiments described herein are provided by way of example only and should not be construed as being limited. While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2009-0127357 | Dec 2009 | KR | national |
10-2010-0047527 | May 2010 | KR | national |