The technology of the disclosure relates generally to a wireless transmission circuit and in particular to a wireless transmission circuit employing a load-line modulation power amplifier circuit.
The fifth generation (5G) system has been widely regarded as the next generation wireless communication system beyond the current third generation (3G) and fourth generation (4G) systems. In this regard, a 5G-capable wireless communication device is expected to achieve higher data rates, improved coverage range, enhanced signaling efficiency, and reduced latency.
The 5G-capable wireless communication device typically includes multiple transmitters to simultaneously transmit multiple 5G radio frequency (RF) signals under such schemes as Carrier Aggregation (CA) and Evolved-Universal Terrestrial Radio Access (E-UTRA) New Radio (NR) Dual Connectivity (DC) (ENDC). Since the transmitters typically transmit the 5G RF signals in a millimeter wave spectrum, the RF signals can be more susceptible to propagation attenuation and interference. To help mitigate propagation attenuation and maintain desirable data throughput, the 5G-capable wireless communication device typically employs multiple power amplifiers to amplify the RF signals to desired power levels before transmitting the RF signals from the transmitters. As such, it is desirable to ensure that the power amplifiers can operate with optimal efficiency, especially when the RF signals are transmitted with different peak-to-average ratios (PARs).
Embodiments of the disclosure relate to efficiency improvement in a wireless transmission circuit. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage. In an embodiment, the power amplifier circuit includes a carrier amplifier and a peak amplifier. The carrier amplifier is always active to amplify the RF signal to an average output power, and the peak amplifier is only active when needed to further amplify the RF signal beyond the average output power. Herein, an activation point of the peak amplifier is dynamically adjusted in accordance with the average output power of the RF signal. As a result, it is possible to eliminate excessive headroom in the APT voltage to thereby improve efficiency of the power amplifier circuit and the wireless transmission circuit as a whole.
In one aspect, a wireless transmission circuit is provided. The wireless transmission circuit includes a power amplifier circuit. The power amplifier circuit includes a carrier amplifier. The carrier amplifier is always activated to amplify an RF signal based on an APT voltage. The power amplifier circuit also includes a peak amplifier. The peak amplifier is activated by a bias voltage to further amplify the RF signal based on the APT voltage. The power amplifier circuit also includes a bias circuit. The bias circuit is configured to generate the bias voltage to thereby activate the peak amplifier when an output power of the RF signal is higher than or equal to a threshold value. The bias circuit is also configured to refrain from generating the bias voltage to thereby deactivate the peak amplifier when the output power of the RF signal is lower than the threshold value. The wireless transmission circuit also includes a power management integrated circuit (PMIC). The PMIC is configured to generate the APT voltage based on a target voltage. The wireless transmission circuit also includes a transceiver circuit. The transceiver circuit is configured to generate and provide the RF signal to the power amplifier circuit. The transceiver circuit is also configured to indicate the output power of the RF signal to the bias circuit. The transceiver circuit is also configured to generate the target voltage based on the output power of the RF signal.
In another aspect, a wireless device is provided. The wireless device includes a wireless transmission circuit. The wireless transmission circuit includes a power amplifier circuit. The power amplifier circuit includes a carrier amplifier. The carrier amplifier is always activated to amplify an RF signal based on an APT voltage. The power amplifier circuit also includes a peak amplifier. The peak amplifier is activated by a bias voltage to further amplify the RF signal based on the APT voltage. The power amplifier circuit also includes a bias circuit. The bias circuit is configured to generate the bias voltage to thereby activate the peak amplifier when an output power of the RF signal is higher than or equal to a threshold value. The bias circuit is also configured to refrain from generating the bias voltage to thereby deactivate the peak amplifier when the output power of the RF signal is lower than the threshold value. The wireless transmission circuit also includes a PMIC. The PMIC is configured to generate the APT voltage based on a target voltage. The wireless transmission circuit also includes a transceiver circuit. The transceiver circuit is configured to generate and provide the RF signal to the power amplifier circuit. The transceiver circuit is also configured to indicate the output power of the RF signal to the bias circuit. The transceiver circuit is also configured to generate the target voltage based on the output power of the RF signal.
In another aspect, a method for improving wireless transmission efficiency is provided. The method includes always activating a carrier amplifier to amplify an RF signal based on an APT voltage. The method also includes activating a peak amplifier by a bias voltage to further amplify the RF signal based on the APT voltage. The method also includes generating the bias voltage to thereby activate the peak amplifier when an output power of the RF signal is higher than or equal to a threshold value. The method also includes refraining from generating the bias voltage to thereby deactivate the peak amplifier when the output power of the RF signal is lower than the threshold value.
Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.
The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Embodiments of the disclosure relate to efficiency improvement in a wireless transmission circuit. The wireless transmission circuit includes a power amplifier circuit that amplifies a radio frequency (RF) signal based on an average power tracking (APT) voltage. In an embodiment, the power amplifier circuit includes a carrier amplifier and a peak amplifier. The carrier amplifier is always active to amplify the RF signal to an average output power, and the peak amplifier is only active when needed to further amplify the RF signal beyond the average output power. Herein, an activation point of the peak amplifier is dynamically adjusted in accordance with the average output power of the RF signal. As a result, it is possible to eliminate excessive headroom in the APT voltage to thereby improve efficiency of the power amplifier circuit and the wireless transmission circuit as a whole.
In an embodiment, the power amplifier circuit 12 can be a Doherty power amplifier circuit. In this regard,
The power amplifier circuit 12 includes a signal input 22 that receives the RF signal 18. The power amplifier circuit 12 also includes a signal output 24 that outputs the amplified RF signal 18 to the load circuit 20, which inherently presents a load impedance ZLOAD to the power amplifier circuit 12.
The power amplifier circuit 12 also includes a carrier amplifier 26 (denoted as “C-PA”) and a peak amplifier 28 (denoted as “P-PA”). The carrier amplifier 26 and the peak amplifier 28, which are coupled in parallel between the signal input 22 and the signal output 24, are configured to collectively amplify the RF signal 18 from the input power PIN to the output power POUT based on the APT voltage VCC.
The power amplifier circuit 12 includes a carrier load-line transfer function (TF) circuit 30 (denoted as “TF-C”) and a peak load-line TF circuit 32 (denoted as “TF-P”). The carrier load-line TF circuit 30 is coupled to an output 34 of the carrier amplifier 26, and the peak load-line TF circuit 32 is coupled to an output 36 of the peak amplifier 28.
The power amplifier circuit 12 also includes an impedance inverter circuit 38 that is coupled between the carrier load-line TF circuit 30 and the peak load-line TF circuit 32. The impedance inverter circuit 38 is configured to create a modulated load impedance ZM based on an equivalent load impedance ZL-EQ. Herein, the equivalent load impedance ZL-EQ represents a total impedance presented to the impedance inverter circuit 38 by the load circuit 20, the peak load-line TF circuit 32, and the peak amplifier 28.
The operational theory and principle behind the power amplifier circuit 12 can be better explained based on an equivalent electrical model. In this regard,
The carrier amplifier 26 is configured to generate a carrier output voltage VOUT-C and a carrier output current IOUT-C. Likewise, the peak amplifier 28 is configured to generate a peak output voltage VOUT-P and a peak output current j*IOUT-P. The carrier load-line TF circuit 30 transforms the carrier output voltage VOUT-C and the carrier output current IOUT-C into a time-variant carrier voltage envelope VM and a time-variant carrier current IM in accordance with Equations 1 and 2, respectively. The peak load-line TF circuit 32 transforms the peak output voltage VOUT-P and the peak output current j*IOUT-P into a time-variant peak voltage envelope VP and a time-variant peak current j*IP in accordance with Equations 3 and 4, respectively.
In the equations above, TFC represents a carrier load-line transfer function implemented by the carrier load-line TF circuit 30, and TFP represents a peak load-line transfer function implemented by the peak load-line TF circuit 32. A relationship between the time-variant peak voltage envelope VP and the time-variant carrier current IM can be expressed in Equation 5 below.
In the Equation 5, Ka represents a coefficient of the impedance inverter circuit 38. The equivalent load impedance ZL-EQ, which represents the total impedance of the load circuit 20, the peak load-line TF circuit 32, and the peak amplifier 28, can be expressed as in Equation 6 below.
In the above equation (Eq. 6), ZLOAD represents the inherent load impedance ZLOAD of the load circuit 20, and ILOAD represents a load current in the load circuit 20. From Equation 6, it can be seen that when j*IP=0, which is an indication that the peak amplifier 28 is deactivated, the equivalent load impedance ZL-EQ will only include the inherent load impedance ZLOAD. However, when j*IP=½ ZLOAD, for example, the equivalent load impedance ZL-EQ will change to 2*ZLOAD. In this regard, the equivalent load impedance ZL-EQ will increase when the peak amplifier 28 is activated.
The impedance inverter circuit 38 is configured to convert the equivalent load impedance ZL-EQ into a modulated load impedance ZM in accordance with Equation 7 below.
From Equation 7, it can be seen that the modulated load impedance ZM will decrease when the equivalent load impedance ZL-EQ increases. In this regard, it is possible to reduce the modulated load impedance ZM by activating the peak amplifier 28. The time-variant carrier voltage envelope VM can be determined based on Equation 8 below.
With reference back to
In the typical operation scheme, when the output power POUT is lower than an average output power PAVG, the peak amplifier 28 is deactivated. Accordingly, the time-variant peak current IP will not be present. The carrier amplifier 26, on the other hand, is active to drive the time-variant carrier voltage envelope VM up toward a maximum (denoted as “Vcc-MAX”) of the APT voltage VCC and increase the time-variant carrier current IM to drive the output power POUT toward the average output power PAVG.
When the output power Pour becomes higher than or equal to the average output power PAVG, the carrier amplifier 26 maintains the time-variant carrier voltage envelope VM at the maximum of the APT voltage VCC (VM=VCC-MAX) but continues to increase the time-variant carrier current IM. In the meantime, the peak amplifier 28 is activated to provide the time-variant peak current IP. Collectively, the time-variant carrier current IM and the time-variant peak current IP can drive the output power POUT toward a peak output power PPEAK. Notably at the peak output power PPEAK, the time-variant carrier current IM will be equal to the time-variant peak current IP.
Under certain dynamic scenarios, the average output power PAVG may need to be reduced to a backoff level PAVG-BACKOFF (e.g., PAVG-BACKOFF=PAVG−3 dB or 6 dB). As such, the peak output power PPEAK will also be reduced to a backoff level PPEAK-BACKOFF (e.g., PPEAK-BACKOFF=PPEAK−3 dB or 6 dB). Accordingly, the APT voltage VCC needed for amplifying the RF signal 18 will be reduced to a backoff level VCC-BACKOFF as well. Under such scenarios, if the peak amplifier 28 is still activated at the original average output power PAVG, the carrier amplifier 26 will drive the time-variant carrier voltage envelope VM toward the maximum of the APT voltage VCC-MAX instead of the backoff APT voltage VCC-BACKOFF, thus causing an excessive APT voltage headroom (VCC-MAX−VCC-BACKOFF). In addition, the carrier amplifier 26 and the peak amplifier 28 will produce an excessive amount of the time-variant carrier current IM and the time-variant peak current IP to drive the output power POUT toward the peak output power PPEAK instead of the backoff peak output power PPEAK-BACKOFF. As a result, the power amplifier circuit 12, and the wireless transmission circuit 10 as a whole, can suffer decreased efficiency and increased power consumption.
In this regard, according to the efficiency improvement scheme described herein, the peak amplifier 28 will be activated at the backoff average output power PAVG-BACKOFF. As illustrated herein, when the output power POUT is lower than the backoff average output power PAVG-BACKOFF, the peak amplifier 28 is deactivated. The carrier amplifier 26, on the other hand, is active to drive the time-variant carrier voltage envelope VM up toward the backoff APT voltage VCC-BACKOFF and increase a time-variant carrier current IM-BACKOFF to drive the output power POUR toward the backoff average output power PAVG-BACKOFF.
When the output power POUR becomes higher than or equal to the backoff average output power PAVG-BACKOFF, the carrier amplifier 26 maintains the time-variant carrier voltage envelope VM at the backoff APT voltage VCC-BACKOFF (VM=VCC-BACKOFF) but continues to increase the time-variant carrier current IM-BACKOFF. In the meantime, the peak amplifier 28 is activated to provide a time-variant peak current IP-BACKOFF. Collectively, the time-variant carrier current IM-BACKOFF and the time-variant peak current IP-BACKOFF can drive the output power POUT toward the backoff peak output power PPEAK-BACKOFF. Notably at the backoff peak output power PPEAK-BACKOFF, the time-variant carrier current IM-BACKOFF will be equal to the time-variant peak current IP-BACKOFF. Thus, by adjusting the activation point of the peak amplifier 28, it is possible to eliminate the excessive APT voltage headroom to thereby improve efficiency of the power amplifier circuit 12 and the wireless transmission circuit 10 as a whole.
Notably herein, either the average output power PAVG or the backoff average output power PAVG-BACKOFF can be referred to as a “threshold value,” depending on how the wireless transmission circuit 10 is configured to operate. Specifically, when the wireless transmission circuit 10 is configured to operate based on the average output power PAVG, the threshold value refers to the average output power PAVG. In contrast, when the wireless transmission circuit 10 is configured to operate based on the backoff average output power PAVG-BACKOFF, the threshold value refers to backoff average output power PAVG-BACKOFF.
With reference back to
In an embodiment, the bias circuit 42 may be configured to adjust the activation point of the peak amplifier 28 on a per-symbol or a per-timeslot basis. In this regard,
The timeslots TSN-1 and TSN are further separated by an extra CP (ΔCP) located between the end time TE of the last OFDM symbol OSM in the preceding timeslot TSN-1 and the start time TS of the first OFDM symbol OS1 in the succeeding timeslot TSN. The extra CP (ΔCP) and the CP of the first OFDM symbol OS1 in the succeeding timeslot TSN collectively provide an extended CP (ECP) (ECP=ΔCP+CP) between the preceding timeslot TSN-1 and the succeeding timeslot TSN. In context of the present disclosure, the duration of each of the OFDM symbols OS1-OSM and the duration of each of the timeslots TSN-1, TSN can both be referred to as a voltage modulation interval, depending on whether the APT voltage VCC is modulated on an inter-symbol or an inter-timeslot basis.
Specifically, when the APT voltage VCC is adapted between each of the OFDM symbols OS1-OSM in each of the timeslots TSN-1, TSN, the voltage modulation interval (also referred to as “inter-symbol voltage modulation interval”) corresponds to the duration of each of the OFDM symbols OS1-OSM. In this regard, the APT voltage VCC transitions (increases or decreases) between consecutive ones of the OFDM symbols OS1-OSM and must be completed within the CP in each of the OFDM symbols OS1-OSM. Accordingly, the CP in each of the OFDM symbols OS1-OSM defines a voltage transition interval (also referred to as “inter-symbol voltage transition interval”) for completing an inter-symbol voltage transition.
In contrast, when the APT voltage VCC is adapted between each of the timeslots TSN-1, TSN, the voltage modulation interval (also referred to as “inter-timeslot voltage modulation interval”) corresponds to the duration of each of the timeslots TSN-1, TSN. In this regard, the APT voltage VCC transitions (increases or decreases) and must be completed within the extended CP (ECP) between the preceding timeslot TSN-1 and the succeeding timeslot TSN. Accordingly, the extended CP (ECP) defines the voltage transition interval (also referred to as “inter-timeslot voltage transition interval”) for inter-timeslot voltage transition.
When the bias circuit 42 is configured to adapt the activation point of the peak amplifier 28 on the per-symbol basis, the bias circuit 42 will receive the indication signal 44 prior to the CP in the succeeding one of each adjacent pair of the OFDM symbols OS1-OSM. As an example, to adapt the activation point of the peak amplifier 28 during the OFDM symbol OS2, the bias circuit 42 will receive the indication signal 44 prior to the end time TE of the OFDM symbol OS1.
When the bias circuit 42 is configured to adapt the activation point of the peak amplifier 28 on the per-timeslot basis, the bias circuit 42 will receive the indication signal 44 prior to a start of the ECP between each adjacent pair of the timeslots TSN-1, TSN. As an example, to adapt the activation point of the peak amplifier 28 during the timeslot TSN, the bias circuit 42 will receive the indication signal 44 prior to the start of the ECP.
In an embodiment, the voltage transition interval (CP or ECP) can be further divided into multiple sections to serve multiple purposes.
Herein, a voltage transition interval (CP for inter-symbol transition and ECP for inter-timeslot transition) can be divided into a first subinterval T1, a second subinterval T2, and a third subinterval T3. The first subinterval T1 may be configured for the PMIC to adapt the APT voltage Vcc and for the bias circuit 42 to adapt the activation point of the peak amplifier 28. The second subinterval T2 may be configured for the transceiver circuit 14 to measure a gain change, an amplitude modulation-amplitude modulation (AM-AM), and/or an amplitude modulation-phase modulation (AM-PM) change at the power amplifier circuit 12. The third subinterval T3 may be configured for the transceiver circuit 14 to apply corrective actions in response to the measured gain change, the measured AM-AM change, and/or the AM-PM change. Such corrective actions may include, for example, digital predistortion (DPD) and adjustment to the input power PIN of the RF signal 18.
To help reduce in-rush current in the power amplifier circuit 12, the efficiency improvement scheme described above may be further adapted to disable the peak amplifier 28 completely when the average output power PAVG is below a predefined power threshold PTH.
Herein, the bias circuit 42 is configured not to generate the bias voltage VBIAS when the output power POUT of the RF signal 18 is lower than the predefined power threshold PTH (POUT<PTH). Accordingly, the peak amplifier 28 will be completely disabled. In the meantime, the PMIC 16 is configured to generate the APT voltage VCC between a minimum voltage VCC-MIN and approximately twice the minimum voltage VCC-MIN (2*VCC-MIN) (VCC-MIN≤Vcc≤2*VCC-MIN).
When the output power POUT is higher than or equal to the predefined threshold power PTH but lower than the backoff average output power PAVG-BACKOFF (PTH≤POUT<PAVG-BACKOFF), the PMIC 16 will be configured to generate the APT voltage VCC between the minimum voltage VCC-MIN and the backoff APT voltage VCC-BACKOFF (VCC-MIN≤VCC≤VCC-BACKOFF). When the output power POUT is higher than or equal to the backoff average output power PAVG-BACKOFF (POUT≥PAVG-BACKOFF), the PMIC 16 will be configured to generate the APT voltage VCC between the minimum voltage VCC-MIN and the maximum APT voltage VCC-MAX (VCC-MIN≤VCC≤VCC-MAX).
The wireless transmission circuit 10 of
Herein, the communication device 100 can be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Bluetooth, and near-field communications. The communication device 100 will generally include a control system 102, a baseband processor 104, transmit circuitry 106, receive circuitry 108, antenna switching circuitry 110, multiple antennas 112, and user interface circuitry 114. In a non-limiting example, the control system 102 can be a field-programmable gate array (FPGA), as an example. In this regard, the control system 102 can include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitry 108 receives radio frequency signals via the antennas 112 and through the antenna switching circuitry 110 from one or more basestations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converters (ADCs).
The baseband processor 104 processes the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processor 104 is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).
For transmission, the baseband processor 104 receives digitized data, which may represent voice, data, or control information, from the control system 102, which it encodes for transmission. The encoded data is output to the transmit circuitry 106, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennas 112 through the antenna switching circuitry 110. The multiple antennas 112 and the replicated transmit circuitry 106 and receive circuitry 108 may provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.
In an embodiment, the wireless transmission circuit 10 can be provided in the communication device 100 to include the transmit circuitry 106, the receive circuitry 108, and the antenna switching circuitry 110. It should be appreciated that the wireless transmission circuit 10 can also be provided in the communication device 100 according to other suitable configurations.
In an embodiment, it is possible to improve efficiency of the wireless transmission circuit 10 of
Herein, the process 200 includes always activating the carrier amplifier 26 to amplify the RF signal 18 based on the APT voltage VCC (step 202). The process 200 also includes activating peak amplifier 28 by the bias voltage VBIAS to further amplify the RF signal 18 based on the APT voltage VCC (step 204). The process 200 also includes generating the bias voltage VBIAS to thereby activate the peak amplifier 28 when the output power POUT of the RF signal 18 is higher than or equal to a threshold value (step 206). The process 200 also includes refraining from generating the bias voltage VBIAS to thereby deactivate the peak amplifier 28 when the output power POUT of the RF signal 18 is lower than the threshold value (step 208).
Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
This application claims the benefit of U.S. provisional patent application Ser. No. 63/533,375, filed on Aug. 18, 2023, the disclosure of which is hereby incorporated herein by reference in its entirety.
Number | Date | Country | |
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63533375 | Aug 2023 | US |