Patent Application
20250077313
Aspects of the present disclosure generally relate to efficient adapter-based context switching in artificial intelligence (AI) acceleration devices.
Artificial neural networks may comprise interconnected groups of artificial neurons (e.g., neuron models). The artificial neural network (ANN) may be a computational device or be represented as a method to be performed by a computational device. Convolutional neural networks (CNNs) are a type of feed-forward ANN. Convolutional neural networks may include collections of neurons that each have a receptive field and that collectively tile an input space. Convolutional neural networks, such as deep convolutional neural networks (DCNs), have numerous applications. In particular, these neural network architectures are used in various technologies, such as image recognition, speech recognition, acoustic scene classification, keyword spotting, autonomous driving, and other classification tasks.
Recently, the use of task-specific adapters in large artificial intelligence (AI) models such as large language models (LLMs) has increased for specific downstream task adaptation. The adapters may vary greatly for the different tasks and may yield effective responses without changes to large AI models. Many of these adapters may also be customized for individuals for an enhanced personal experience.
However, many neural network frameworks on edge devices may only support static graphs in pursuit of optimum efficiency and may disregard support for dynamic modifications to the neural network. As such, switching adapters in edge devices to improve performance on different tasks may be challenging.
The present disclosure is set forth in the independent claims, respectively. Some aspects of the disclosure are described in the dependent claims.
In various aspects of the present disclosure, a processor-implemented method includes analyzing a first neural network model and one or more adapters. The first neural network model is pre-trained and each of the one or more adapters is configured with an architecture and parameters for performing a different downstream task of a set of downstream tasks. The processor-implemented method also includes defining a default adapter based on a capacity of the one or more adapters. The processor-implemented method further includes applying the default adapter to one or more layers of the first neural network model during a context switch to replace an adapter of the one or more adapters for a different task. A static graph that corresponds to the first neural network model remains unchanged.
Other aspects of the present disclosure are directed to an apparatus including means for analyzing a first neural network model and one or more adapters. The first neural network model is pre-trained and each of the one or more adapters is configured with an architecture and parameters for performing a different downstream task of a set of downstream tasks. The apparatus also includes means for defining a default adapter based on a capacity of the one or more adapters. The apparatus further includes means for applying the default adapter to one or more layers of the first neural network model during a context switch to replace an adapter of the one or more adapters for a different task. A static graph that corresponds to the first neural network model remains unchanged.
In various aspects of the present disclosure, a non-transitory computer-readable medium with non-transitory program code recorded thereon is disclosed. The program code is executed by a processor and includes program code to analyze a first neural network model and one or more adapters. The first neural network model is pre-trained and each of the one or more adapters is configured with an architecture and parameters for performing a different downstream task of a set of downstream tasks. The program code also includes program code to define a default adapter based on a capacity of the one or more adapters. The program code further includes program code to apply the default adapter to one or more layers of the first neural network model during a context switch to replace an adapter of the one or more adapters for a different task. A static graph that corresponds to the first neural network model remains unchanged.
Some aspects of the present disclosure are directed to an apparatus having at least one memory and one or more processors coupled to the at least one memory. The processor(s) is configured to analyze a first neural network model and one or more adapters. The first neural network model is pre-trained and each of the one or more adapters is configured with an architecture and parameters for performing a different downstream task of a set of downstream tasks. The processor(s) is also configured to define a default adapter based on a capacity of the one or more adapters. The processor(s) is further configured to apply the default adapter to one or more layers of the first neural network model during a context switch to replace an adapter of the one or more adapters for a different task. A static graph that corresponds to the first neural network model remains unchanged.
Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.
The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.
Based on the teachings, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth. In addition, the scope of the disclosure is intended to cover such an apparatus or method practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of a claim.
The word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Although particular aspects are described, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.
Artificial Intelligence (AI) acceleration devices are a class of specialized hardware accelerators designed to increase processing speed and efficiency for machine learning workloads and applications. AI acceleration devices may include dedicated processors to accelerate machine learning computations. AI acceleration devices may be employed in time consuming parts of an AI application such as for generating an inference. In this case, computations for generating an inference may be offloaded to the AI accelerator to reduce latency and improve performance of AI applications.
An adapter is a small set of weights that are newly initialized and added to layers of a neural network. Adapters may be applied to different layers of a pre-trained neural network and may have different sizes. The adapters may provide an alternative to fine-tuning the pre-trained neural network. Rather than fine-tuning the pre-trained neural network, the added weights are trained while the weights of the pre-trained neural network are fixed. The adapters may be trained for specific downstream tasks or may be customized for an enhanced personal performance.
As described, many neural network frameworks may only support static graphs and may not support dynamic modifications to the neural network. A naïve solution to address this problem may involve merging (e.g., folding) a mergeable adapter to a static large AI model during context switching. However, doing so may involve altering a majority of the parameters of the large AI model. Consequently, the cost of the conventional context switch approach may be prohibitively high. Furthermore, the conventional context switch approach may not be applicable to adapters that cannot be folded.
Accordingly, aspects of the present disclosure are directed to performing efficient context switching using various adapters and large AI models on AI acceleration devices that support static graphs. In various aspects, a default adapter may be defined with a maximum capacity. The term “maximum capacity” in this context may refer to the ability of an adapter to encompass both a number of layers and the number of parameters. For example, in a model composed of 10 layers, if adapter A fits into a second layer and a third layer, both having a parameter size of 10 and adapter B fits into a third layer and a fourth layer with a parameter size of 20, then the default adapter with maximum capacity may cover the second layer, the third layer and the fourth layer. In this case, the second layer has a parameter size of at least 10, and the third layer and fourth layer each have a parameter size of at least 20. Thus, the maximum capacity may comprise the ability to accommodate the total number of layers as well as the total number of parameters across such layers.
Static graphs provide support for devices with the default adapter and create static graphs with large AI models. Static graphs may be generated with the default adapter that has a maximum capacity.
Particular aspects of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In some examples, the described techniques (e.g., defining a default adapter, and/or applying the default adapter to a pre-trained neural network model during a context switch without changing parameters of the pre-trained neural network model) may reduce memory consumption, model latency, and training time.
The SOC 100 may also include additional processing blocks tailored to specific functions, such as a GPU 104, a DSP 106, a connectivity block 110, which may include fifth generation (5G) connectivity, fourth generation long term evolution (4G LTE) connectivity, Wi-Fi connectivity, USB connectivity, Bluetooth connectivity, and the like, and a multimedia processor 112 that may, for example, detect and recognize gestures. In one implementation, the NPU 108 is implemented in the CPU 102, DSP 106, and/or GPU 104. The SOC 100 may also include a sensor processor 114, image signal processors (ISPs) 116, and/or navigation module 120, which may include a global positioning system.
The SOC 100 may be based on an ARM instruction set. In aspects of the present disclosure, the instructions loaded into the general-purpose processor 102 may include code to analyze a first neural network model and one or more adapters. The first neural network model is pre-trained and each of the one or more adapters is configured with an architecture and parameters for performing a different downstream task of a set of downstream tasks. The general-purpose processor 102 may also include code to define a default adapter based on a maximum capacity of the one or more adapters. The general-purpose processor 102 may further include code to apply the default adapter to one or more layers of the first neural network model during a context switch to replace an adapter of the one or more adapters for a different task. A graph corresponding to the first neural network model is unchanged.
Deep learning architectures may perform an object recognition task by learning to represent inputs at successively higher levels of abstraction in each layer, thereby building up a useful feature representation of the input data. In this way, deep learning addresses a major bottleneck of traditional machine learning. Prior to the advent of deep learning, a machine learning approach to an object recognition problem may have relied heavily on human engineered features, perhaps in combination with a shallow classifier. A shallow classifier may be a two-class linear classifier, for example, in which a weighted sum of the feature vector components may be compared with a threshold to predict to which class the input belongs. Human engineered features may be templates or kernels tailored to a specific problem domain by engineers with domain expertise. Deep learning architectures, in contrast, may learn to represent features that are similar to what a human engineer might design, but through training. Furthermore, a deep network may learn to represent and recognize new types of features that a human might not have considered.
A deep learning architecture may learn a hierarchy of features. If presented with visual data, for example, the first layer may learn to recognize relatively simple features, such as edges, in the input stream. In another example, if presented with auditory data, the first layer may learn to recognize spectral power in specific frequencies. The second layer, taking the output of the first layer as input, may learn to recognize combinations of features, such as simple shapes for visual data or combinations of sounds for auditory data. For instance, higher layers may learn to represent complex shapes in visual data or words in auditory data. Still higher layers may learn to recognize common visual objects or spoken phrases.
Deep learning architectures may perform especially well when applied to problems that have a natural hierarchical structure. For example, the classification of motorized vehicles may benefit from first learning to recognize wheels, windshields, and other features. These features may be combined at higher layers in different ways to recognize cars, trucks, and airplanes.
Neural networks may be designed with a variety of connectivity patterns. In feed-forward networks, information is passed from lower to higher layers, with each neuron in a given layer communicating to neurons in higher layers. A hierarchical representation may be built up in successive layers of a feed-forward network, as described above. Neural networks may also have recurrent or feedback (also called top-down) connections. In a recurrent connection, the output from a neuron in a given layer may be communicated to another neuron in the same layer. A recurrent architecture may be helpful in recognizing patterns that span more than one of the input data chunks that are delivered to the neural network in a sequence. A connection from a neuron in a given layer to a neuron in a lower layer is called a feedback (or top-down) connection. A network with many feedback connections may be helpful when the recognition of a high-level concept may aid in discriminating the particular low-level features of an input.
The connections between layers of a neural network may be fully connected or locally connected.
One example of a locally connected neural network is a convolutional neural network.
One type of convolutional neural network is a deep convolutional network (DCN).
The DCN 200 may be trained with supervised learning. During training, the DCN 200 may be presented with an image, such as the image 226 of a speed limit sign, and a forward pass may then be computed to produce an output 222. The DCN 200 may include a feature extraction section and a classification section. Upon receiving the image 226, a convolutional layer 232 may apply convolutional kernels (not shown) to the image 226 to generate a first set of feature maps 218. As an example, the convolutional kernel for the convolutional layer 232 may be a 5×5 kernel that generates 28×28 feature maps. In the present example, because four different feature maps are generated in the first set of feature maps 218, four different convolutional kernels were applied to the image 226 at the convolutional layer 232. The convolutional kernels may also be referred to as filters or convolutional filters.
The first set of feature maps 218 may be subsampled by a max pooling layer (not shown) to generate a second set of feature maps 220. The max pooling layer reduces the size of the first set of feature maps 218. That is, a size of the second set of feature maps 220, such as 14×14, is less than the size of the first set of feature maps 218, such as 28×28. The reduced size provides similar information to a subsequent layer while reducing memory consumption. The second set of feature maps 220 may be further convolved via one or more subsequent convolutional layers (not shown) to generate one or more subsequent sets of feature maps (not shown).
In the example of
In the present example, the probabilities in the output 222 for “sign” and “60” are higher than the probabilities of the others of the output 222, such as “30,” “40,” “50,” “70,” “80,” “90,” and “100”. Before training, the output 222 produced by the DCN 200 may likely be incorrect. Thus, an error may be calculated between the output 222 and a target output. The target output is the ground truth of the image 226 (e.g., “sign” and “60”). The weights of the DCN 200 may then be adjusted so the output 222 of the DCN 200 is more closely aligned with the target output.
To adjust the weights, a learning algorithm may compute a gradient vector for the weights. The gradient may indicate an amount that an error would increase or decrease if the weight were adjusted. At the top layer, the gradient may correspond directly to the value of a weight connecting an activated neuron in the penultimate layer and a neuron in the output layer. In lower layers, the gradient may depend on the value of the weights and on the computed error gradients of the higher layers. The weights may then be adjusted to reduce the error. This manner of adjusting the weights may be referred to as “back propagation” as it involves a “backward pass” through the neural network.
In practice, the error gradient of weights may be calculated over a small number of examples, so that the calculated gradient approximates the true error gradient. This approximation method may be referred to as stochastic gradient descent. Stochastic gradient descent may be repeated until the achievable error rate of the entire system has stopped decreasing or until the error rate has reached a target level. After learning, the DCN 200 may be presented with new images (e.g., the speed limit sign of the image 226) and a forward pass through the DCN 200 may yield an output 222 that may be considered an inference or a prediction of the DCN 200.
Deep belief networks (DBNs) are probabilistic models comprising multiple layers of hidden nodes. DBNs may be used to extract a hierarchical representation of training data sets. A DBN may be obtained by stacking up layers of Restricted Boltzmann Machines (RBMs). An RBM is a type of artificial neural network that can learn a probability distribution over a set of inputs. Because RBMs can learn a probability distribution in the absence of information about the class to which each input should be categorized, RBMs are often used in unsupervised learning. Using a hybrid unsupervised and supervised paradigm, the bottom RBMs of a DBN may be trained in an unsupervised manner and may serve as feature extractors, and the top RBM may be trained in a supervised manner (on a joint distribution of inputs from the previous layer and target classes) and may serve as a classifier.
DCNs are networks of convolutional networks, configured with additional pooling and normalization layers. DCNs have achieved state-of-the-art performance on many tasks. DCNs can be trained using supervised learning in which both the input and output targets are known for many exemplars and are used to modify the weights of the network by use of gradient descent methods.
DCNs may be feed-forward networks. In addition, as described above, the connections from a neuron in a first layer of a DCN to a group of neurons in the next higher layer are shared across the neurons in the first layer. The feed-forward and shared connections of DCNs may be exploited for fast processing. The computational burden of a DCN may be much less, for example, than that of a similarly sized neural network that comprises recurrent or feedback connections.
The processing of each layer of a convolutional network may be considered a spatially invariant template or basis projection. If the input is first decomposed into multiple channels, such as the red, green, and blue channels of a color image, then the convolutional network trained on that input may be considered three-dimensional, with two spatial dimensions along the axes of the image and a third dimension capturing color information. The outputs of the convolutional connections may be considered to form a feature map in the subsequent layer, with each element of the feature map (e.g., 220) receiving input from a range of neurons in the previous layer (e.g., feature maps 218) and from each of the multiple channels. The values in the feature map may be further processed with a non-linearity, such as a rectification, max(0, x). Values from adjacent neurons may be further pooled, which corresponds to down sampling, and may provide additional local invariance and dimensionality reduction. Normalization, which corresponds to whitening, may also be applied through lateral inhibition between neurons in the feature map.
Although only two of the convolution blocks 354A, 354B are shown, the present disclosure is not so limiting, and instead, any number of the convolution blocks 354A, 354B may be included in the DCN 350 according to design preference.
The convolution layers 356 may include one or more convolutional filters, which may be applied to the input data to generate a feature map. The normalization layer 358 may normalize the output of the convolution filters. For example, the normalization layer 358 may provide whitening or lateral inhibition. The max pooling layer 360 may provide down sampling aggregation over space for local invariance and dimensionality reduction.
The parallel filter banks, for example, of a deep convolutional network may be loaded on a CPU 102 or GPU 104 of an SOC 100 (e.g.,
The DCN 350 may also include one or more fully connected layers 362 (FC1 and FC2). The DCN 350 may further include a logistic regression (LR) layer 364. Between each layer 356, 358, 360, 362, 364 of the DCN 350 are weights (not shown) that are to be updated. The output of each of the layers (e.g., 356, 358, 360, 362, 364) may serve as an input of a succeeding one of the layers (e.g., 356, 358, 360, 362, 364) in the DCN 350 to learn hierarchical feature representations from input data 352 (e.g., images, audio, video, sensor data and/or other input data) supplied at the first of the convolution blocks 354A. The output of the DCN 350 is a classification score 366 for the input data 352. The classification score 366 may be a set of probabilities, where each probability is the probability of the input data including a feature from a set of features.
The AI application 402 may be configured to call functions defined in a user space 404 that may, for example, provide for the detection and recognition of a scene indicative of the location at which the computational device including the architecture 400 currently operates. The AI application 402 may, for example, configure a microphone and a camera differently depending on whether the recognized scene is an office, a lecture hall, a restaurant, or an outdoor setting such as a lake. The AI application 402 may make a request to compiled program code associated with a library defined in an AI function application programming interface (API) 406. This request may ultimately rely on the output of a deep neural network configured to provide an inference response based on video and positioning data, for example.
The run-time engine 408, which may be compiled code of a runtime framework, may be further accessible to the AI application 402. The AI application 402 may cause the run-time engine 408, for example, to request an inference at a particular time interval or triggered by an event detected by the user interface of the AI application 402. When caused to provide an inference response, the run-time engine 408 may in turn send a signal to an operating system in an operating system (OS) space 410, such as a Kernel 412, running on the SOC 420. In some examples, the Kernel 412 may be a LINUX Kernel. The operating system, in turn, may cause a continuous relaxation of quantization to be performed on the CPU 422, the DSP 424, the GPU 426, the NPU 428, or some combination thereof. The CPU 422 may be accessed directly by the operating system, and other processing blocks may be accessed through a driver, such as a driver 414, 416, or 418 for, respectively, the DSP 424, the GPU 426, or the NPU 428. In the exemplary example, the deep neural network may be configured to run on a combination of processing blocks, such as the CPU 422, the DSP 424, and the GPU 426, or may be run on the NPU 428.
As described, various aspects of the present disclosure are directed to performing efficient context switching using various adapters and large AI models on AI acceleration devices that support static graphs.
Each of the conventional adapters 510a-c may be designed for a specific downstream task and may have different architectures and weights. That is, the conventional adapters 510a-c may also be applied to different layers and may have different sizes. For example, conventional adapter 510a may be designed specifically for task A and may be applied to layers 504a and 504c. Conventional adapter 510c may be designed specifically for task C and may applied to layers 504a and 504b. Conventional adapter 510b may designed for task B and may be applied to all layers 504a-c.
During a context switch (e.g., switching to a different task), the conventional adapters 510a-c may merge to the large AI model 502, which may involve changing a majority of the weights of the large AI model 502. Unlike the conventional adapters 510a-c, the default adapter 500 is flexible and may replace adapters (e.g., task-specific adapters) of different sizes and may be applied to different layers. For example, the default adapter 500 may be configured to cover each (or some) of the conventional adapters 510a-c.
The default adapter 500 may be generated by analyzing the large AI model 502 and one or more of the conventional adapters 510a-c. For example, the number and or types of layers to which the conventional adapters are applied and/or the number of parameters in each layer may be determined. A capacity of the default adapter 500 may then be determined based on the analysis. For instance, the largest number of layers and the largest number of parameters among the one or more conventional adapters 510a-c may be determined. The capacity of the default adapter 500 may be defined to accommodate the largest number of parameters and the largest number of layers.
Having defined the default adapter 500, the default adapter 500 may be applied to the layers (e.g., 504a-c) of the large AI model 502. The parameters of the large AI model 502 (e.g., for a particular task) may be fixed such that only the parameters (e.g., weights) of the default adapter 500 may be changed during training. Thus, when the context is switched (e.g., switching from task A to task B) and the default adapter 500 is deployed, a static graph for the pre-trained large AI model 502 may remain unchanged and the parameters (e.g., weights) of the default adapter 500, which may be stored in memory, for example, may be changed. That is, rather than retraining the large AI model 502, only the parameters of the default adapter 500 are retrained.
On the other hand, when the tasks do not demand use of a specific adapter for the target task, the default adapter 500 may be applied. In this case, the AI model (e.g., 502) may use the default adapter 500 to perform the target task (e.g., inference).
When the default adapter 500 is applied in server environments, the static graph may support dynamic inference using the machine learning development framework. For example, when utilizing a framework that supports dynamic inference (e.g., TensorFlow or PyTorch) several adapters may be dynamically selected to perform inference. As such, an appropriate adapter may be selected and used for each inference without performing a compilation step, thereby enabling increased flexibility and adaptability in server environments.
However, to apply the default adapter 500 on edge devices, a device-specific static graph may be generated. The edge device may comprise (but is not limited to) a mobile device, an Internet of things (IoT) device, or an autonomous vehicle, for instance. The large AI model (e.g., 502) as well as several adapters (e.g., 510a-c) may be analyzed. The structure of the default adapter (e.g., 500) may be defined to cover the maximum capacity (e.g., number of layers and parameters) of the analyzed adapters. That is, in order to define the default adapter with a capacity (e.g., maximum capacity), an analysis may be performed to determine the position and size of the default adapter. As such, the default adapter may be determined to cover all layers and/or parameters. In some aspects, the analysis may, for instance, include mapping the network structure of each of the task-specific adapters, quantifying the respective sizes of the task-specific adapters in terms of the number of layers and parameters, and then designing the default adapter such that the default adapter can accommodate these mapped structures and parameters. In some aspects, the analysis may be based on other performance metrics of the adapters.
An AI model including the large AI model (e.g., 502) and the default adapter (e.g., 500) may be defined. Then, the AI model including the large AI model (e.g., 502) and the default adapter (e.g., 500) may be compiled to convert the AI model to a static graph for a target edge device.
In some aspects, the default adapter (e.g., 500) may be utilized to generate one or more new adapters for new tasks. For instance, if the device-specific static graph has already been shared and the AI model has already been deployed on an edge device, a new adapter may be added. In this case, an adapter structure may be defined within the capacity range of the default adapter (e.g., 500). As such, the new adapter may be compatible with the default adapter (e.g., 500). The new adapter may be trained for the new target task. In turn, the new adapter (excluding the AI model) may be distributed to the target devices. Thereafter, a context switch may be conducted on the target devices using the new adapter for the application.
Accordingly, the default adapter (e.g., 500) may be used during context switching to beneficially reduce computation cost and memory consumption during a context switch because only the adapter weights in memory may be changed. In contrast, the cost of conventional approaches may involve larger memory consumption because many of the model parameters (e.g., weights) may be changed (e.g., with merging operations).
Moreover, various aspects of the present disclosure may simplify context switching in edge devices by providing a multi-compatible adapter approach. Providing a maximum capacity default adapter may ensure efficient and cost-effective context-switching. Furthermore, by preserving the static graph and altering only the default adapter parameters, the disruption in functionality during context switching may be reduced.
As shown in
At block 704, the processor defines a default adapter based on a capacity of the one or more adapters. As described with reference to
At block 706, the processor applies the default adapter to one or more layers of the first neural network model during a context switch to replace an adapter of the one or more adapters for a different task. A static graph corresponding to the first neural network model remains unchanged. For instance, as described with reference to
Implementation examples are included in the following numbered clauses.
In some aspects, the analyzing means, defining means, and/or applying means may be the CPU 102/422, program memory associated with the CPU 102/422, the dedicated memory block 118, fully connected layers 362, GPU 104/426, NPU 108/428 and/or the routing connection processing unit 216 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.
The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus-function components with similar numbering.
As used, the term “determining” encompasses a wide variety of actions. For example, “determining” may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Additionally, “determining” may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, “determining” may include resolving, selecting, choosing, establishing, and the like.
As used, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.
The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
The methods disclosed comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.
The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or special-purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.
In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.
The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture. Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.
The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module. Furthermore, it should be appreciated that aspects of the present disclosure result in improvements to the functioning of the processor, computer, machine, or other system implementing such aspects.
If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Additionally, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects, computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer-readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.
Thus, certain aspects may comprise a computer program product for performing the operations presented. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described. For certain aspects, the computer program product may include packaging material.
Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described. Alternatively, various methods described can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described to a device can be utilized.
It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes, and variations may be made in the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.
