Patent Application
20110157151
None.
The subject matter described herein relates generally to the field of displays and more particularly to an efficient luminous display which may be used in electronic devices.
In some instances motion blur in an LDC display is due to the “sample and hold” nature of operation of the display. This interacts with a smooth pursuit of moving objects by the human visual system resulting in blurred images. One approach to resolve this is to increase the frame rate of the display by a factor of two and alternate black frames with the image frames. This produces a display with an impulse response, but results in a fifty percent loss of luminous efficiency. Thus, the backlight power must be doubled to return the display to full luminance.
One approach to providing stereoscopic three-dimensional images is through the use of shutter glasses to demultiplex a series of left eye and right eye images shown in a rapid alternating sequence. Under typical LCD display timing it is not viable to fully separate the left eye and right eye images with an LCD display. In order to provide the correct image to each eye the period of time when the display is not updated, commonly referred to as the VBlank period, must be extended and the period of time when the display is updated must be reduced. A high performance display system may have the VBlank period extended to 33% of the available frame time and the shutter glasses synchronized to open during VBlank. In this condition the total luminance efficiency is reduced to 33% relative to the available frame time.
Accordingly techniques to implement an efficient luminous display may find utility.
The detailed description is described with reference to the accompanying figures.
Described herein are exemplary displays and systems and methods to implement an efficient luminous display which may be used in electronic devices. In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the particular embodiments.
Referring to
A diffuser 142 is positioned adjacent the backlight assembly 134. In some embodiments, diffuser 142 may also act as a polarizer to polarize light emitted by light-emitting diodes (LEDs) in the backlight assembly. A LCD module 144 is positioned adjacent diffuser 142. In some embodiments, LCD module may be a twisted nematic LCD, an In-plane switching LCD, or a vertical alignment (VA) LCD and may comprise other components for the display image formation such as tft backplane, polarizer, analyzer, color filter array, etc. In some embodiments, a light directing film 146 may be positioned adjacent the LCD to enhance the brightness of the display.
In some embodiments, timing controller 132 controls the timing parameters of operations of the display assembly 100, while backlight controller 133 drives the backlight assembly 134 to produce a peak luminance which is inversely proportional to the duty cycle of the backlight assembly when adjusted for the maximum display luminosity. This may be accomplished by pulsing the backlight assembly 134 at proportionally larger currents and/or by increasing the number of LEDs in the backlight assembly 134. Further, in some embodiments the timing controller 132 may adjust various timing parameters, for example the timing duration of the VBlank period.
In some embodiments techniques to implement an efficient luminous display may be implemented in a conventional LCD display to reduce power consumption while reducing motion blur on the display. This technique may be referred to as motion blur mitigation (MBM). Aspects of motion blur mitigation will be described with reference to
In some embodiments an LCD monitor may implement motion blur mitigation procedures which enhance the efficiency of the display. Referring to
In some embodiments the backlight controller may drive the backlight assembly at relatively high power levels, assuming there is no control of the peak current that can be driven to the light emitting diodes (LEDs) in the backlight assembly. The maximum panel brightness that can be obtained is therefore proportional to the VBlank period over the frame period relative to the peak brightness.
Referring back to
In some embodiments the register values are calculated as follows. A value T1 corresponds to the VActive period as a value between 0 and 1. Similarly, a value T2 corresponds to VBlank period as a value between 0 and 1. Neither T1 nor T2 may be zero. The sum of T1+T2 must equal 1, i.e., T1 and T2 represent a percent of the frame time. A value D1 corresponds to backlight PWM duty cycle during VActive as a value between 0 and 1, and a value D2 corresponds to a backlight PWM duty cycle during Vblank as a value between 0 and 1. Given these parameters, the total percent brightness of the display may be determined by:
T1*D1+T2*D2=Total percent brightness Eq. 1
The maximum motion blur mitigation occurs when D1=0 and D2=1 therefore register calculations must satisfy
T1*D1+T2*D2=T2 Eq. 2
The minimum motion blur mitigation occurs when D1=D2=T2 therefore 0<D1<T2 (See
D2=1−(T1*D1)/T2 Eq. 3
For a virtual motion blur mitigation control (MBM) that varies from 0 (off) to 1, the value D1 may be determined by:
D1=(1−MBM)*T2 Eq. 4
The resulting values for D1 and D2 may be scaled to register value requirements. By way of example, in a system in which the VBlank period is 40% of the time, T1=0.6 and T2=0.4, and in which motion blur mitigation (MBM2) is off (i.e., MBM2=0):
D1=(1−MBM2)*T2
D1=(1−0)*0.4
D1=0.4
D2=1−(T1*D1)/T2
D2=1−(0.6*0.4)/0.4
D2=0.4
By contrast, in a system in which the VBlank period is 40% of the time, T1=0.6 and T2=0.4, and in which motion blur mitigation (MBM) is fully on (i.e., MBM=1):
D1=(1−MBM)*T2
D1=(1−1)*0.4
D1=0
D2=1−(T1*D1)/T2
D2=1−(0.6*0)/0.4
D2=1
In a system in which the VBlank period is 40% of the time, T1=0.6 and T2=0.4, and in which motion blur mitigation (MBM) is set to 50% (i.e., MBM=0.5):
D1=(1−MBM)*T2
D1=(1−0.5)*0.4
D1=0.2
D2=1−(T1*D1)/T2
D2=1−(0.6*0.2)/0.4
D2=0.7
One skilled in the art will recognize that using PWM to control the brightness is not necessarily the only way. The D1 and D2 registers represent a proportional brightness. A general brightness control which is also possible through the D1 and D2 registers as a multiplicative factor. The virtual MBM control can be used to balance the MBM effect against the potential for perceived flicker in the display. At a refresh rate of 60 Hz, some people may notice flicker. For faster refresh rates this is not a problem.
In other embodiments techniques to implement an efficient luminous display may find application in display devices configured to present stereoscopic, three-dimensional (3D) images. General operations of such embodiments will be described with reference to
Referring now to
At operation 535 the complete left-eye image is presented on the display, at which point another power activation cycle is initiated (operation 540) to illuminate the backlight assembly. Contemporaneously, a shutter cycle may be initiated. At operation 550 the power activation cycle is terminated when the next image refresh cycle begins (operation 550). The operations depicted in
As described above, in some embodiments a display as described herein may be implemented in an electronic device, e.g., a computer system.
Electrical power may be provided to various components of the computing device 602 (e.g., through a computing device power supply 606) from one or more of the following sources: one or more battery packs, an alternating current (AC) outlet (e.g., through a transformer and/or adaptor such as a power adapter 604), automotive power supplies, airplane power supplies, and the like. In some embodiments, the power adapter 604 may transform the power supply source output (e.g., the AC outlet voltage of about 110 VAC to 240 VAC) to a direct current (DC) voltage ranging between about 7 VDC to 12.6 VDC. Accordingly, the power adapter 604 may be an AC/DC adapter.
The computing device 602 may also include one or more central processing unit(s) (CPUs) 608. In some embodiments, the CPU 608 may be one or more processors in the Pentium® family of processors including the Pentium® II processor family, Pentium® III processors, Pentium® IV, or CORE2 Duo processors available from Intel® Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used, such as Intel's Itanium®, XEON™, and Celeron® processors. Also, one or more processors from other manufactures may be utilized. Moreover, the processors may have a single or multi core design.
A chipset 612 may be coupled to, or integrated with, CPU 608. The chipset 612 may include a memory control hub (MCH) 614. The MCH 614 may include a memory controller 616 that is coupled to a main system memory 618. The main system memory 618 stores data and sequences of instructions that are executed by the CPU 608, or any other device included in the system 600. In some embodiments, the main system memory 618 includes random access memory (RAM); however, the main system memory 618 may be implemented using other memory types such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Additional devices may also be coupled to the bus 610, such as multiple CPUs and/or multiple system memories.
The MCH 614 may also include a graphics interface 620 coupled to a graphics accelerator 622. In some embodiments, the graphics interface 620 is coupled to the graphics accelerator 622 via an accelerated graphics port (AGP). In some embodiments, a display (such as a flat panel display) 640 may be coupled to the graphics interface 620 through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display. The display 640 signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display.
A hub interface 624 couples the MCH 614 to an platform control hub (PCH) 626. The PCH 626 provides an interface to input/output (I/O) devices coupled to the computer system 600. The PCH 626 may be coupled to a peripheral component interconnect (PCI) bus. Hence, the PCH 626 includes a PCI bridge 628 that provides an interface to a PCI bus 630. The PCI bridge 628 provides a data path between the CPU 608 and peripheral devices. Additionally, other types of I/O interconnect topologies may be utilized such as the PCI Express™ architecture, available through Intel® Corporation of Santa Clara, Calif.
The PCI bus 630 may be coupled to an audio device 632 and one or more disk drive(s) 634. Other devices may be coupled to the PCI bus 630. In addition, the CPU 608 and the MCH 614 may be combined to form a single chip. Furthermore, the graphics accelerator 622 may be included within the MCH 614 in other embodiments.
Additionally, other peripherals coupled to the PCH 626 may include, in various embodiments, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), universal serial bus (USB) port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), and the like. Hence, the computing device 602 may include volatile and/or nonvolatile memory.
The terms “logic instructions” as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and embodiments are not limited in this respect.
The terms “computer readable medium” as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and embodiments are not limited in this respect.
The term “logic” as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and embodiments are not limited in this respect.
Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.
In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.
Reference in the specification to “one embodiment” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.
Although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.
