The present invention relates generally to computer data systems and, in particular, to maintaining and updating entries in a memory list.
In a data processing system, or in a component such as a disk control unit, customer data is frequently moved between storage elements, such as external storage drives, internal processor memory, conventional volatile RAM, non-volatile memory, etc. A list is typically maintained of entries which are associated with the data. Entries may include memory addresses, pointers or other means of identifying the data which is being moved. Entry lists conventionally have been built and maintained through instructions executed by a controller processor. However, building and maintaining a list consumes valuable processor resources. Moreover, spurious writes to the list may be undetected or an entry in the list may be corrupted, possibly leading to data being lost or unavailable and placing the integrity of the list in question.
Consequently, a need remains for a means of maintaining an entry list which is efficient and relieves the controller processor from at least some of its former responsibilities. There remains a further need to maintain an entry list while enhancing the ability to detect errors.
The present invention provides a protocol for managing memory entry lists in a data management system, such as a disk control unit. Preferably, the protocol is implemented substantially in hardware, thus freeing other system resources to execute other processes. Additionally, improved error correction may be performed as the list is being built and updated.
The list is initially built by adding new entries to pre-allocated space, each space having an address. A first entry is added to space having a first address and a pointer is set to reference the first address. If error checking is enabled, an error check value is generated. The next entry is added to space having the next address, the pointer is incremented to point to the next address and the error check value is updated. The process continues until all entries have been added to the list.
The list is updated by first determining if the update is the removal of an interstitial entry or of the last (most recently added) entry. If the update is the removal of an interstitial entry, that entry is removed from the list and, if error checking is enabled, the error check value is updated. The last entry is then written to the space vacated by the removed interstitial entry and a predetermined value which is neutral relative to the error checking procedure (such as all zeros) is written to the space vacated by the former last entry. The pointer is decremented to now reference the address “below” the former last entry; the entry stored in this address is the new last entry.
If the update is the removal of the last entry, the last entry is removed from the list and, if error checking is enabled, the error check value is updated. A predetermined neutral value is then written to the space vacated by the last entry and the pointer is decremented to now reference the address “below” the former last entry; the entry stored in this address is the new last entry.
The protocol, including error checking if enabled, is efficient and may be implemented substantially in hardware.
The present invention provides an improved entry list management protocol and employs hardware logic to reduce spurious writes to the list and to reduce the burden on the controller processor. Optionally, the present invention may also include improved error detection to enhance the integrity of the memory list.
The entry list 110 may reside in a memory (including the memory device 106) or may reside in a register. The entry list 110 initially comprises empty spaces which have been allocated to the list 110, each of which has an address, such as O-n, for a predetermined number of future entries.
As illustrated in FIGS. 2A-E, when the entry list 110 is being built each new entry is added to the empty space with the lowest address in the list 110. This is the most recently added entry and is designated the “last entry”. Preferably, each new entry is processed through EC logic 108 (
After the entry list has been built, entries may be updated or removed. FIGS. 3A-D illustrate the manner in which an interstitial entry, such as EAQ 200C in address space 02 may be removed according to the present invention. First, a new entry 200G is compared with the last entry 200F; both entries are the same (HYH). The target address of the new entry 200G is 02 and is compared with valid list addresses. If the target address is not a valid list address, an error is noted. Because the target address is determined to be a valid address, the old (interstitial) entry 200C is then removed from the list 110 and processed through the EC logic 108 which updates the error check value (
FIGS. 4A-D illustrate the manner in which the last entry, such as HYH 200F may be removed according to the present invention. First, the target address of the new entry is confirmed to be the address of the last entry 05 and the new entry data itself 000 is confirmed to be neutral with respect to the error checking logic 108 (
If an existing entry is to be updated (510), the last entry in the list 110 is read (516) and replaced in the last space with a value, such as all 0's, which is neutral relative to the error checking logic 108 (518) and the address pointer (which actually designates the addresses of the entry spaces) is decremented (520) such that the next entry now becomes the last entry. A comparison is then made between the new entry and the old last entry (522). If the two do not match, an error is logged (524) and the process returns (560). If the two entries match and if the error checking logic is enabled (526), the entry being updated is read (528) and processed through the error checking logic to update the error check value (530). If the error checking assist is disabled (526), or after the error check value has been updated, the new entry is written (stored) in the existing space (532) and control returns (560).
If a new entry is to be added to the list and there is space available at the end of the list (512), the new entry is written to the empty space (534) and the address pointer is incremented (536), thereby making the new entry the Last Entry and adjusting the addresses of the other entries. If the error checking logic is enabled (538), the new entry is processed and the error check value updated (540). If the error checking logic is disabled, or upon updating the error check value if the error checking logic is enabled, control returns (560).
If the assist logic is disabled (508), a decision is made whether the error checking logic is enabled (542). If not, the entry is merely written to the list (544) and control returns (560). Otherwise, the entry is and processed through the error checking logic (546) before being written to the list (544). Control is then returned (560).
Consequently, because the read, compare, error detection and write operations are performed by the entry list assist logic 110, the burden on other system resources is reduced. Additionally, the list protocol reduces the risk of unintended writes to the entry list, thereby improving its reliability.
The objects of the invention have been fully realized through the embodiments disclosed herein. Those skilled in the art will appreciate that the various aspects of the invention may be achieved through different embodiments without departing from the essential function of the invention. The particular embodiments are illustrative and not meant to limit the scope of the invention as set forth in the following claims.
The present application is related to commonly-assigned and co-pending United States Application Serial Number 10/______ [IBM Docket #TUC920040128], entitled ______, filed on the filing date hereof, which application is incorporated herein by reference in its entirety.