Claims
- 1. A method for managing data in an integrated circuit, comprising:
(a) receiving data from one or more sources within the integrated circuit; (b) storing the data in a buffer memory; (c) transferring the data from the buffer to an external memory location at a predetermined point; and repeating (a) through (c).
- 2. The method of claim 1, wherein receiving data comprises receiving data from one or more modules.
- 3. The method of claim 2, wherein the one or more modules generate statistical information relating to particular parameters of the integrated circuit.
- 4. The method of claim 1, wherein receiving data comprises receiving data from a plurality of modules.
- 5. The method of claim 1, wherein storing the data in the buffer memory comprises generating write control signals between the buffer memory and a controller.
- 6. The method of claim 1, wherein transferring the data from the buffer memory to an external memory comprises generating read control signals between the buffer memory and an external memory interface.
- 7. The method of claim 1, wherein storing the data in the buffer memory comprises performing a multiplexing operation on the data from plural sources to the buffer memory.
- 8. The method of claim 1, wherein the predetermined point is determined by the amount of data in the buffer memory.
- 9. The method of claim 6, wherein the predetermined point is determined by the availability of an external device.
- 10. A system for managing data in an integrated circuit, comprising:
a system memory; at least one source of data; a buffer memory; and a controller connected to the at least one source, wherein the controller is operative to receive data from the at least one source and transfer the data to the buffer, wherein at a predetermined point the buffer is instructed to transfer the data to the system memory.
- 11. The system of claim 10, further comprising at least two sources of data.
- 12. The system of claim 10, wherein the controller comprises an output selector that is designed to perform a multiplexing operation of the incoming data from the plural sources.
- 13. The system of claim 10, wherein the buffer memory is of a size between about 100 and about 3000 bytes.
- 14. The system of claim 10, wherein the buffer memory and controller are operative to transmit write control signals therebetween to coordinate the writing of data to the buffer.
- 15. The system of claim 10, wherein the buffer memory and an interface are operative to transmit read control signals therebetween to coordinate the transfer of data from the buffer to the system memory.
- 16. The system of claim 15, wherein the buffer memory is operative to transmit a read control signal upon the accumulation of a predetermined amount of data in the buffer memory.
- 17. The system of claim 15, wherein the interface is operative to transmit a read control signal upon determining the availability of an external device.
PRIORITY CLAIM
[0001] This application claims priority based on U.S. Provisional Patent Application Ser. No. 60/183,615, filed on Feb. 18, 2000.
Reissues (1)
|
Number |
Date |
Country |
Parent |
60183615 |
Feb 2000 |
US |
Child |
09785794 |
Feb 2001 |
US |