Claims
- 1. A method for decoding a received word, comprising:
calculating a syndrome of the received word as a plurality of binary element vectors; generating respective logarithms of the binary element vectors; and determining, in response to the logarithms, an indication of a position of an erroneous bit in the received word.
- 2. A method according to claim 1, wherein the received word is formed from a code word of a Bose, Chaudhuri, and Hocquenghem (BCH) code having an error-correction value greater than or equal to two, and wherein the plurality is equal to the error-correction value.
- 3. A method according to claim 2, wherein the error-correction value is equal to two, wherein generating respective logarithms comprises generating a first logarithm log p and a second logarithm log q, and wherein determining the indication comprises generating an index I to an error-locating table from an expression (log q−3log p).
- 4. A method according to claim 3, and comprising making a comparison of the index I with zero, and in response to the comparison determining that the erroneous bit comprises a single erroneous bit.
- 5. A method according to claim 1, and comprising recovering an information message from the received word, and applying the indication of the position of the erroneous bit to the information message so as to determine an information word.
- 6. A method according to claim 1, wherein generating the respective logarithms comprises using each of the binary vectors as an index to a Galois Field logarithm table.
- 7. A method according to claim 6, wherein the received word is formed from a code word of a BCH code having a block length equal to 2m−1, wherein m is an integer greater than or equal to three, wherein a number of elements in each binary element vector is equal to m, and wherein the Galois Field logarithm table comprises elements of order GF(2m).
- 8. A method according to claim 7, and comprising providing adjustment circuitry which is adapted to adjust the indication of the position of the erroneous bit for m being an odd integer or an even integer.
- 9. A method according to claim 1, wherein determining the indication comprises generating an index to an error-locating table as a pre-determined function of the respective logarithms.
- 10. A method according to claim 9, wherein the received word comprises a known-erroneous-bit-position word, wherein the position of the erroneous bit in the known-erroneous-bit-position word is known, and comprising generating the error-locating table using the known-erroneous-bit-position word.
- 11. A method according to claim 10, wherein the known-erroneous-bit-position word comprises a normalized error vector.
- 12. A method according to claim 9, wherein the received word is formed from a code word of a BCH code having an error-correction value, and wherein the error-locating table is implemented to generate the indication as a multiplicity of pointers, the multiplicity being equal to the error-correction value.
- 13. A method according to claim 9, wherein generating the index comprises generating an adjustment to the index in response to at least one of the plurality of binary element vectors and the index.
- 14. A method according to claim 9, and comprising adjusting an output of the error-locating table in response to at least one of the plurality of binary element vectors and the index.
- 15. A method according to claim 1, wherein generating the respective logarithms comprises generating an index to an error-locating table as a pre-determined function of the respective logarithms, and wherein determining the indication comprises:
determining a plurality of pointers to respective positions of erroneous bits; and receiving from the error-locating table the plurality of pointers.
- 16. A method according to claim 15, and comprising adjusting the plurality of pointers in response to an adjusting logarithm comprised in the logarithms, so as to determine respective positions of the erroneous bits.
- 17. Apparatus for decoding a received word, comprising:
a processor which is adapted to:
calculate a syndrome of the received word as a plurality of binary element vectors, generate respective logarithms of the binary element vectors, and determine, in response to the logarithms, an indication of a position of an erroneous bit in the received word.
- 18. Apparatus according to claim 17, wherein the received word is formed from a code word of a Bose, Chaudhuri, and Hocquenghem (BCH) code having an error-correction value greater than or equal to two, and wherein the plurality is equal to the error-correction value.
- 19. Apparatus according to claim 18, wherein the error-correction value is equal to two, wherein the respective logarithms comprise a first logarithm log p and a second logarithm log q, and wherein the indication comprises an index I to an error-locating table including an expression (log q−3log p).
- 20. Apparatus according to claim 19, wherein the processor is adapted to make a comparison of the index I with zero, and in response to the comparison to determine that the erroneous bit comprises a single erroneous bit.
- 21. Apparatus according to claim 17, wherein the processor is adapted to recover an information message from the received word, and to apply the indication of the position of the erroneous bit to the information message so as to determine an information word.
- 22. Apparatus according to claim 17, wherein the processor is adapted to generate the respective logarithms using each of the binary element vectors as an index to a Galois Field logarithm table.
- 23. Apparatus according to claim 22, wherein the received word is formed from a code word of a BCH code having a block length equal to 2m−1, wherein m is an integer greater than or equal to three, wherein a number of elements in each binary element vector is equal to m, and wherein the Galois Field logarithm table comprises elements of order GF(2m).
- 24. Apparatus according to claim 23, and comprising adjustment circuitry which is adapted to adjust the indication of the position of the erroneous bit for m being an odd integer or an even integer.
- 25. Apparatus according to claim 17, wherein the indication comprises an index to an error-locating table as a pre-determined function of the respective logarithms.
- 26. Apparatus according to claim 25, wherein the received word comprises a known-erroneous-bit-position word, wherein the position of the erroneous bit in the known-erroneous-bit-position word is known, and wherein the processor is adapted to generate the error-locating table using the known-erroneous-bit-position word.
- 27. Apparatus according to claim 26, wherein the known-erroneous-bit-position word comprises a normalized error vector.
- 28. Apparatus according to claim 25, wherein the received word is formed from a code word of a BCH code having an error-correction value, and wherein the error-locating table is implemented to generate the indication as a multiplicity of pointers, the multiplicity being equal to the error-correction value.
- 29. Apparatus according to claim 25, and comprising adjustment circuitry which is adapted to generate an adjustment to the index in response to at least one of the plurality of binary element vectors and the index.
- 30. Apparatus according to claim 25, and comprising adjustment circuitry which is adapted to adjust an output of the error-locating table in response to at least one of the plurality of binary element vectors and the index.
- 31. Apparatus according to claim 17, wherein the processor is adapted to generate an index to an error-locating table as a pre-determined function of the respective logarithms, and wherein the indication comprises a plurality of pointers to respective positions of erroneous bits, and wherein the processor is adapted to receive from the error-locating table the plurality of pointers.
- 32. Apparatus according to claim 31, wherein the processor is adapted to adjust the plurality of pointers in response to an adjusting logarithm comprised in the logarithms, so as to determine respective positions of the erroneous bits.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Patent Application No. 60/350,652 filed Jan. 22, 2002, which is incorporated herein by reference.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60350652 |
Jan 2002 |
US |