Patent Application
20250124535
The present disclosure relates generally to processing systems, and more particularly, to one or more techniques for display processing.
Computing devices often perform graphics and/or display processing (e.g., utilizing a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones such as smartphones, embedded systems, personal computers, tablet computers, and video game consoles. GPUs are configured to execute a graphics processing pipeline that includes one or more processing stages, which operate together to execute graphics processing commands and output a frame. A central processing unit (CPU) may control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern day CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize the GPU during execution. A display processor may be configured to convert digital information received from a CPU to analog values and may issue commands to a display panel for displaying the visual content. A device that provides content for visual presentation on a display may utilize a CPU, a GPU, and/or a display processor.
Current techniques for a multiple partial update of a frame may miss an update when regions of interest (ROIs) of the frame are too close to one another. There is a need for improved techniques pertaining to multiple partial updates of frames.
The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for display processing are provided. The apparatus includes a memory; and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to: obtain a software-based indication that indicates to start an execution of command packets; execute, based on the obtained software-based indication, a first set of command packets associated with a first region of interest (ROI) of a frame that is to be updated; obtain a hardware-based indication that indicates that the first set of command packets associated with the first ROI of the frame has been executed; and execute, based on the obtained hardware-based indication, a second set of command packets associated with a second ROI of the frame that is to be updated.
To the accomplishment of the foregoing and related ends, the one or more aspects include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents.
Various aspects of systems, apparatuses, computer program products, and methods are described more fully hereinafter with reference to the accompanying drawings. This disclosure may, however, be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein one skilled in the art should appreciate that the scope of this disclosure is intended to cover any aspect of the systems, apparatuses, computer program products, and methods disclosed herein, whether implemented independently of, or combined with, other aspects of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth herein. In addition, the scope of the disclosure is intended to cover such an apparatus or method which is practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth herein. Any aspect disclosed herein may be embodied by one or more elements of a claim.
Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to particular benefits, uses, or objectives. Rather, aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, processing systems, networks, and transmission protocols, some of which are illustrated by way of example in the figures and in the following description. The detailed description and drawings are merely illustrative of this disclosure rather than limiting, the scope of this disclosure being defined by the appended claims and equivalents thereof.
Several aspects are presented with reference to various apparatus and methods. These apparatus and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, and the like (collectively referred to as “elements”). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether such elements are implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system.
By way of example, an element, or any portion of an element, or any combination of elements may be implemented as a “processing system” that includes one or more processors (which may also be referred to as processing units). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems-on-chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other suitable hardware configured to perform the various functionality described throughout this disclosure. One or more processors in the processing system may execute software. Software can be construed broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software components, applications, software applications, software packages, routines, subroutines, objects, executables, threads of execution, procedures, functions, etc., whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise.
The term application may refer to software. As described herein, one or more techniques may refer to an application (e.g., software) being configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., on-chip memory of a processor, system memory, or any other memory). Hardware described herein, such as a processor may be configured to execute the application. For example, the application may be described as including code that, when executed by the hardware, causes the hardware to perform one or more techniques described herein. As an example, the hardware may access the code from a memory and execute the code accessed from the memory to perform one or more techniques described herein. In some examples, components are identified in this disclosure. In such examples, the components may be hardware, software, or a combination thereof. The components may be separate components or sub-components of a single component.
In one or more examples described herein, the functions described may be implemented in hardware, software, or any combination thereof. If implemented in software, the functions may be stored on or encoded as one or more instructions or code on a computer-readable medium. Computer-readable media includes computer storage media. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include a random access memory (RAM), a read-only memory (ROM), an electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, combinations of the aforementioned types of computer-readable media, or any other medium that can be used to store computer executable code in the form of instructions or data structures that can be accessed by a computer.
As used herein, instances of the term “content” may refer to “graphical content,” an “image,” etc., regardless of whether the terms are used as an adjective, noun, or other parts of speech. In some examples, the term “graphical content,” as used herein, may refer to a content produced by one or more processes of a graphics processing pipeline. In further examples, the term “graphical content,” as used herein, may refer to a content produced by a processing unit configured to perform graphics processing. In still further examples, as used herein, the term “graphical content” may refer to a content produced by a graphics processing unit.
A multiple partial frame update may refer to a feature that supports updating regions of interest (ROIs) of a frame, as opposed to the entirety of a frame. As ROIs of a frame are updated in a multiple partial frame update (as opposed to all regions of the frame), multiple partial frame updates may conserve computing resources and/or battery power of a device. A multiple partial frame update may be useful in scenarios in which there is little content change between two successive frames. A device may perform a multiple partial frame update for ROIs of a frame based on (multiple) software based indications received for each ROI of the frame. However, the (multiple) software based indications may be associated with latency which may cause the device to miss updating an ROI. This may prevent the device from successfully performing the multiple partial frame update for the frame and/or may lead to tearing effects when the frame is displayed.
Various technologies pertaining to efficient multiple partial updates in display processing are described herein. In an example, an apparatus (e.g., a display processor) obtains a software-based indication that indicates to start an execution of command packets. The apparatus executes, based on the obtained software-based indication, a first set of command packets associated with a first region of interest (ROI) of a frame that is to be updated. The apparatus obtains a hardware-based indication that indicates that the first set of command packets associated with the first ROI of the frame has been executed. The apparatus executes, based on the obtained hardware-based indication, a second set of command packets associated with a second ROI of the frame that is to be updated. Vis-à-vis executing the second set of command packets based on the obtained hardware based indication, the apparatus may perform a multiple partial frame update with reduced latency compared to another apparatus that executes the second set of command packets based on a (second) software based indication. The reduced latency may enable the apparatus to successfully perform a multiple partial frame update for a frame when ROIs of the frame are relatively close to one another and may prevent or mitigate tearing effects when the frame is displayed.
Multiple partial update may refer to a feature that allows processing in regions of interest (ROIs) which may be useful for low power mode. However, when ROIs are too close to each other, multiple partial update may not be used because the update may be missed due to interrupt service request (ISR) latency and configuration execution latency. In one aspect described herein, a lookup table direct memory access (LUTDMA), which may be a faster engine than an advance high-performance bus (AHB) interface, may program an ROI configuration faster, thus reducing configuration execution latency. ISR Latency may be removed as the LUTDMA prepares a packet for all the ROIs at the beginning of the frame, and thus a LUTDMA based design may not have to wait for ISR latency before the LUTDMA can configure a next ROI. The first trigger for LUTDMA may be software (SW) controlled, and successive triggers for the LUTDMA may be generated in hardware (HW) based on completion of a previous ROI (i.e., ROI_DONE_irq).
The examples describe herein may refer to a use and functionality of a graphics processing unit (GPU). As used herein, a GPU can be any type of graphics processor, and a graphics processor can be any type of processor that is designed or configured to process graphics content. For example, a graphics processor or GPU can be a specialized electronic circuit that is designed for processing graphics content. As an additional example, a graphics processor or GPU can be a general purpose processor that is configured to process graphics content.
The processing unit 120 may include an internal memory 121. The processing unit 120 may be configured to perform graphics processing using a graphics processing pipeline 107. The content encoder/decoder 122 may include an internal memory 123. In some examples, the device 104 may include a processor, which may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120 before the frames are displayed by the one or more displays 131. While the processor in the example content generation system 100 is configured as a display processor 127, it should be understood that the display processor 127 is one example of the processor and that other types of processors, controllers, etc., may be used as substitute for the display processor 127. The display processor 127 may be configured to perform display processing. For example, the display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by the processing unit 120. The one or more displays 131 may be configured to display or otherwise present frames processed by the display processor 127. In some examples, the one or more displays 131 may include one or more of a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.
Memory external to the processing unit 120 and the content encoder/decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder/decoder 122. For example, the processing unit 120 and the content encoder/decoder 122 may be configured to read from and/or write to external memory, such as the system memory 124. The processing unit 120 may be communicatively coupled to the system memory 124 over a bus. In some examples, the processing unit 120 and the content encoder/decoder 122 may be communicatively coupled to the internal memory 121 over the bus or via a different connection.
The content encoder/decoder 122 may be configured to receive graphical content from any source, such as the system memory 124 and/or the communication interface 126. The system memory 124 may be configured to store received encoded or decoded graphical content. The content encoder/decoder 122 may be configured to receive encoded or decoded graphical content, e.g., from the system memory 124 and/or the communication interface 126, in the form of encoded pixel data. The content encoder/decoder 122 may be configured to encode or decode any graphical content.
The internal memory 121 or the system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or the system memory 124 may include RAM, static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable ROM (EPROM), EEPROM, flash memory, a magnetic data media or an optical storage media, or any other type of memory. The internal memory 121 or the system memory 124 may be a non-transitory storage medium according to some examples. The term “non-transitory” may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. However, the term “non-transitory” should not be interpreted to mean that internal memory 121 or the system memory 124 is non-movable or that its contents are static. As one example, the system memory 124 may be removed from the device 104 and moved to another device. As another example, the system memory 124 may not be removable from the device 104.
The processing unit 120 may be a CPU, a GPU, a GPGPU, or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into a motherboard of the device 104. In further examples, the processing unit 120 may be present on a graphics card that is installed in a port of the motherboard of the device 104, or may be otherwise incorporated within a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, ASICs, FPGAs, arithmetic logic units (ALUs), DSPs, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the processing unit 120 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 121, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.
The content encoder/decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder/decoder 122 may be integrated into a motherboard of the device 104. The content encoder/decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuitry, or any combinations thereof. If the techniques are implemented partially in software, the content encoder/decoder 122 may store instructions for the software in a suitable, non-transitory computer-readable storage medium, e.g., internal memory 123, and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.
In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving function described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information, e.g., eye or head position information, rendering commands, and/or location information, from another device. The transmitter 130 may be configured to perform any transmitting function described herein with respect to the device 104. For example, the transmitter 130 may be configured to transmit information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving function and/or transmitting function described herein with respect to the device 104.
Referring again to
A device, such as the device 104, may refer to any device, apparatus, or system configured to perform one or more techniques described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer such as a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer, an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device such as a portable video game device or a personal digital assistant (PDA), a wearable computing device such as a smart watch, an augmented reality device, or a virtual reality device, a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an in-vehicle computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more techniques described herein. Processes herein may be described as performed by a particular component (e.g., a GPU) but in other embodiments, may be performed using other components (e.g., a CPU) consistent with the disclosed embodiments.
GPUs can process multiple types of data or data packets in a GPU pipeline. For instance, in some aspects, a GPU can process two types of data or data packets, e.g., context register packets and draw call data. A context register packet can be a set of global state information, e.g., information regarding a global register, shading program, or constant data, which can regulate how a graphics context will be processed. For example, context register packets can include information regarding a color format. In some aspects of context register packets, there can be a bit or bits that indicate which workload belongs to a context register. Also, there can be multiple functions or programming running at the same time and/or in parallel. For example, functions or programming can describe a certain operation, e.g., the color mode or color format. Accordingly, a context register can define multiple states of a GPU.
Context states can be utilized to determine how an individual processing unit functions, e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor, and/or in what mode the processing unit functions. In order to do so, GPUs can use context registers and programming data. In some aspects, a GPU can generate a workload, e.g., a vertex or pixel workload, in the pipeline based on the context register definition of a mode or state. Certain processing units, e.g., a VFD, can use these states to determine certain functions, e.g., how a vertex is assembled. As these modes or states can change, GPUs may need to change the corresponding context. Additionally, the workload that corresponds to the mode or state may follow the changing mode or state.
As shown in
GPUs can render images in a variety of different ways. In some instances, GPUs can render an image using direct rendering and/or tiled rendering. In tiled rendering GPUs, an image can be divided or separated into different sections or tiles. After the division of the image, each section or tile can be rendered separately. Tiled rendering GPUs can divide computer graphics images into a grid format, such that each portion of the grid, i.e., a tile, is separately rendered. In some aspects of tiled rendering, during a binning pass, an image can be divided into different bins or tiles. In some aspects, during the binning pass, a visibility stream can be constructed where visible primitives or draw calls can be identified. A rendering pass may be performed after the binning pass. In contrast to tiled rendering, direct rendering does not divide the frame into smaller bins or tiles. Rather, in direct rendering, the entire frame is rendered at a single time (i.e., without a binning pass). Additionally, some types of GPUs can allow for both tiled rendering and direct rendering (e.g., flex rendering).
In some aspects, GPUs can apply the drawing or rendering process to different bins or tiles. For instance, a GPU can render to one bin, and perform all the draws for the primitives or pixels in the bin. During the process of rendering to a bin, the render targets can be located in GPU internal memory (GMEM). In some instances, after rendering to one bin, the content of the render targets can be moved to a system memory and the GMEM can be freed for rendering the next bin. Additionally, a GPU can render to another bin, and perform the draws for the primitives or pixels in that bin. Therefore, in some aspects, there might be a small number of bins, e.g., four bins, that cover all of the draws in one surface. Further, GPUs can cycle through all of the draws in one bin, but perform the draws for the draw calls that are visible, i.e., draw calls that include visible geometry. In some aspects, a visibility stream can be generated, e.g., in a binning pass, to determine the visibility information of each primitive in an image or scene. For instance, this visibility stream can identify whether a certain primitive is visible or not. In some aspects, this information can be used to remove primitives that are not visible so that the non-visible primitives are not rendered, e.g., in the rendering pass. Also, at least some of the primitives that are identified as visible can be rendered in the rendering pass.
In some aspects of tiled rendering, there can be multiple processing phases or passes. For instance, the rendering can be performed in two passes, e.g., a binning, a visibility or bin-visibility pass and a rendering or bin-rendering pass. During a visibility pass, a GPU can input a rendering workload, record the positions of the primitives or triangles, and then determine which primitives or triangles fall into which bin or area. In some aspects of a visibility pass, GPUs can also identify or mark the visibility of each primitive or triangle in a visibility stream. During a rendering pass, a GPU can input the visibility stream and process one bin or area at a time. In some aspects, the visibility stream can be analyzed to determine which primitives, or vertices of primitives, are visible or not visible. As such, the primitives, or vertices of primitives, that are visible may be processed. By doing so, GPUs can reduce the unnecessary workload of processing or rendering primitives or triangles that are not visible.
In some aspects, during a visibility pass, certain types of primitive geometry, e.g., position-only geometry, may be processed. Additionally, depending on the position or location of the primitives or triangles, the primitives may be sorted into different bins or areas. In some instances, sorting primitives or triangles into different bins may be performed by determining visibility information for these primitives or triangles. For example, GPUs may determine or write visibility information of each primitive in each bin or area, e.g., in a system memory. This visibility information can be used to determine or generate a visibility stream. In a rendering pass, the primitives in each bin can be rendered separately. In these instances, the visibility stream can be fetched from memory and used to remove primitives which are not visible for that bin.
Some aspects of GPUs or GPU architectures can provide a number of different options for rendering, e.g., software rendering and hardware rendering. In software rendering, a driver or CPU can replicate an entire frame geometry by processing each view one time. Additionally, some different states may be changed depending on the view. As such, in software rendering, the software can replicate the entire workload by changing some states that may be utilized to render for each viewpoint in an image. In certain aspects, as GPUs may be submitting the same workload multiple times for each viewpoint in an image, there may be an increased amount of overhead. In hardware rendering, the hardware or GPU may be responsible for replicating or processing the geometry for each viewpoint in an image. Accordingly, the hardware can manage the replication or processing of the primitives or triangles for each viewpoint in an image.
A GPU may be included in devices that provide content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphical data for display on a computing device (e.g., the device 104), which may be a computer workstation, a mobile phone, a smartphone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, and the like. Operations of the GPU 310 may be controlled based on one or more graphics processing commands provided by a CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the concurrently executed multiple applications may utilize the GPU 310 simultaneously. Processing techniques may be performed via the processing unit 120 output a frame over physical or wireless communication channels.
The system memory 124, which may be executed by the processing unit 120, may include a user space 320 and a kernel space 325. The user space 320 (sometimes referred to as an “application space”) may include software application(s) and/or application framework(s). For example, software application(s) may include operating systems, media applications, graphical applications, workspace applications, etc. Application framework(s) may include frameworks used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. The kernel space 325 may further include a display driver 330. The display driver 330 may be configured to control the display processor 127. For example, the display driver 330 may cause the display processor 127 to compose a frame and transmit the data for the frame to a display.
The display processor 127 includes a display control block 335 and a display interface 340. The display processor 127 may be configured to manipulate functions of the display(s) 131 (e.g., based on an input received from the display driver 330). The display control block 335 may be further configured to output image frames to the display(s) 131 via the display interface 340. In some examples, the display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of the system memory 124 by the processing unit 120.
The display interface 340 may be configured to cause the display(s) 131 to display image frames. The display interface 340 may output image data to the display(s) 131 according to an interface protocol, such as, for example, the MIPI DSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display(s) 131, may be configured in accordance with MIPI DSI standards. The MIPI DSI standard supports a video mode and a command mode. In examples where the display(s) 131 is/are operating in video mode, the display processor 127 may continuously refresh the graphical content of the display(s) 131. For example, the entire graphical content may be refreshed per refresh cycle (e.g., line-by-line). In examples where the display(s) 131 is/are operating in command mode, the display processor 127 may write the graphical content of a frame to a buffer 350.
In some such examples, the display processor 127 may not continuously refresh the graphical content of the display(s) 131. Instead, the display processor 127 may use a vertical synchronization (Vsync) pulse to coordinate rendering and consuming of graphical content at the buffer 350. For example, when a Vsync pulse is generated, the display processor 127 may output new graphical content to the buffer 350. Thus, generation of the Vsync pulse may indicate that current graphical content has been rendered at the buffer 350.
Frames are displayed at the display(s) 131 based on a display controller 345, a display client 355, and the buffer 350. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display(s) 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.
The display client 355 may be associated with a touch panel that senses interactions between a user and the display(s) 131. As the user interacts with the display(s) 131, one or more sensors in the touch panel may output signals to the display controller 345 that indicate which of the one or more sensors have sensor activity, a duration of the sensor activity, an applied pressure to the one or more sensor, etc. The display controller 345 may use the sensor outputs to determine a manner in which the user has interacted with the display(s) 131. The display(s) 131 may be further associated with/include other devices, such as a camera, a microphone, and/or a speaker, that operate in connection with the display client 355.
Some processing techniques of the device 104 may be performed over three stages (e.g., stage 1: a rendering stage; stage 2: a composition stage; and stage 3: a display/transfer stage). However, other processing techniques may combine the composition stage and the display/transfer stage into a single stage, such that the processing technique may be executed based on two total stages (e.g., stage 1: the rendering stage; and stage 2: the composition/display/transfer stage). During the rendering stage, the GPU 310 may process a content buffer based on execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stage(s), pixel elements may be assembled to form a frame that is transferred to a physical display panel/subsystem (e.g., the displays 131) that displays the frame.
Instructions executed by a CPU (e.g., software instructions) or a display processor may cause the CPU or the display processor to search for and/or generate a composition strategy for composing a frame based on a dynamic priority and runtime statistics associated with one or more composition strategy groups. A frame to be displayed by a physical display device, such as a display panel, may include a plurality of layers. Also, composition of the frame may be based on combining the plurality of layers into the frame (e.g., based on a frame buffer). After the plurality of layers are combined into the frame, the frame may be provided to the display panel for display thereon. The process of combining each of the plurality of layers into the frame may be referred to as composition, frame composition, a composition procedure, a composition process, or the like.
A frame composition procedure or composition strategy may correspond to a technique for composing different layers of the plurality of layers into a single frame. The plurality of layers may be stored in double data rate (DDR) memory. Each layer of the plurality of layers may further correspond to a separate buffer. A composer or hardware composer (HWC) associated with a block or function may determine an input of each layer/buffer and perform the frame composition procedure to generate an output indicative of a composed frame. That is, the input may be the layers and the output may be a frame composition procedure for composing the frame to be displayed on the display panel.
Some aspects of display processing may utilize different types of mask layers, e.g., a shape mask layer. A mask layer is a layer that may represent a portion of a display or display panel. For instance, an area of a mask layer may correspond to an area of a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of a display area. Also, for certain portions of a display area, the content of different mask layers may overlap with one another. Accordingly, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.
In an example pertaining to the partial frame update 502, a device (e.g., the device 104, the display processor 127) may obtain a first frame 504 and a second frame 506, where the first frame 504 and the second frame 506 may be successive frames in a set of frames, that is, the first frame 504 may be displayed immediately prior to the second frame 506.
As illustrated in
The diagram 600 further depicts a timing diagram 614 representing three ROI updates (e.g., an update for the zeroth ROI 606, an update for the first ROI 608, and an update for the second ROI 610) for a zeroth frame 616. The display processor may prepare a configuration (referred to hereafter as “Config_Prepare 618”) for the multiple partial frame update for the zeroth ROI 606. After the Config_Prepare 618, the display processor may execute the configuration (referred to hereafter as “Config_Execution 620”) for the zeroth ROI 606. The Config_Execution 620 for the zeroth ROI 606 may trigger an ROI start process (referred to hereafter as “ROI_START 622”). The ROI START 622 may cause a region of interest data transfer (referred to hereafter as “ROI Transfer 624”) with respect to the zeroth ROI 606. The ROI_Transfer 624 may occur at the beginning of a start window 627. Upon completion of the ROI_Transfer 624, an interrupt service request (referred to hereafter as “ROI_DONE/IRQ 626”) may be generated for the zeroth ROI 606. The ROI_DONE/IRQ 626 for the zeroth ROI 606 may be serviced via interrupt servicing. Config_Prepare 618 for the first ROI 608 may not begin until the interrupt servicing is performed for the zeroth ROI 606, which may cause an interrupt servicing request (ISR) latency 628. The display processor may perform similar functionality as described above with respect to the first ROI 608 and the second ROI 610. The display processor may perform processing for a first frame 630 that follows the first frame upon the ROI_Transfer 624 for the second ROI 610. The zeroth frame may also undergo a vertical synchronization (VSYNC 632).
The LUTDMA engine 802 may include or be associated with a command queue 806 and command descriptor random access memory (RAM) 808. In one aspect, the command queue 806 may be stored in the command descriptor RAM 808. A software configuration 810 may cause command descriptors 812 to be stored in the command descriptor RAM 808. The command descriptors 812 may define an address of and a number of the command packets 814 that are stored in DDR memory 816. The command packets 814 may include information about an operation code (OPCODE), a block that is to be programmed to facilitate presentation of a frame (e.g., facilitate a partial frame update or a multiple partial frame update), and corresponding software register values. While stored in the DDR memory 816, the command packets 814 may be encoded. Aspects pertaining to the command descriptors 812 and the command packets 814 will be discussed in greater detail below. Upon reception of a start trigger 818, the LUTDMA engine 802 may store the command descriptors 812 in the command queue 806. Based on the command descriptors 812 stored in the command queue 806, at 820, the LUTDMA engine 802 may fetch (i.e., retrieve) the command packets 814 from the DDR memory 816. At 822, the LUTDMA engine 802 may decode the (fetched) command packets 814 and execute the (fetched) command packets 814. Executing the (fetched) command packets 814 may program registers associated with a frame (e.g., registers associated with a partial frame update, registers associated with a multiple partial frame update, etc.).
When the LUTDMA engine 802 receives a start trigger, the LUTDMA engine 802 may execute CDs stored in the command queue 902. In one aspect, the start trigger may be software controlled. In one aspect, in a multiple partial frame update scenario, the LUTDMA engine 802 may be triggered via a software trigger for each ROI configuration update. For instance, if a frame includes a first ROI, a second ROI, and a third ROI, the LUTDMA engine 802 may receive a first software trigger for the first ROI, a second software trigger for the second ROI, and a third software trigger for the third ROI. Software based triggers may be associated with latency. Multiple software triggers for a frame may impact an ability of the LUTDMA engine 802 to perform a multiple partial frame update.
In one aspect, a hardware based trigger for an ROI 1002 for a frame may be a write pointer interrupt request (referred to hereafter as “WR_PTR_irq 1004”). The WR_PTR_irq 1004 may be generated once a counter (e.g., a write pointer counter, referred to hereafter as “WR_PTR_cntr”) reaches a software programmable counter value. Stated differently, ROI_DONE_irq may be based on the WR_PTR_irq 1004.
In one aspect, a hardware based trigger for an ROI 1002 for a frame may be a ping pong buffer done interrupt request (referred to hereafter as “PP_DONE_irq 1006”). PP_DONE_irq 1006 may be generated once a last pixel of the ROI 1002 is removed (i.e., drained) from ping pong buffers. A ping pong buffer may refer to a double buffer. The ping pong buffers may be last pipeline buffers in a display processor (e.g., the display processor 127, the display processor 404). Stated differently, ROI_DONE_irq may be based on the PP_DONE_irq 1006. In one aspect, WR_PTR_irq 1004 may occur (i.e., be generated) prior to PP_DONE_irq 1006 occurring (i.e., prior to PP_DONE_irq 1006 being generated).
When the LUTDMA engine 802 is triggered for ROI updates via hardware triggers (e.g., WR_PTR_irq 1004, PP_DONE_irq 1006), the LUTDMA engine 802 may be said to be running in automode. A software register bit (i.e., “MODE_SEL”) may indicate that the LUTDMA engine 802 is running in automode (which may also be referred to as AUTOMODE or AUTO_MODE). Table 1 below details aspects pertaining to automode.
In an example, a value (e.g., zero or one) of a LUTDMA_AUTOMODE_EN register 1008 may determine whether the LUTDMA engine 802 runs in automode. A value (e.g., zero or one) of a MODE_SEL register 1010 may determine which hardware based trigger (e.g., WR_PTR_irq 1004 or PP_DONE_irq 1006) is to be used for a next frame. Stated differently, during automode, the LUTDMA engine 802 may be triggered either by WR_PTR_irq 1004 or PP_DONE_irq 1006 based on a value of the MODE_SEL register 1010. To disable automode once all ROIs for a frame have been configured, a last command packet of a last ROI may include an indication that a value of the LUTDMA_AUTOMODE_EN register 1008 is to be set to zero. Once the LUTDMA engine 802 is out of automode, the LUTDMA engine 802 may be triggered via a software based trigger for a next frame.
In an example, the LUTDMA engine 802 may include a multiplexer (referred to hereafter as “MUX 1012”). The LUTDMA engine 802 may combine a value of the LUTDMA_AUTOMODE_EN register 1008 and a value of the MODE_SEL register 1010. The MUX 1012 may take, as input, at least one of WR_PTR_irq 1004, PP_DONE_irq 1006, a software (SW) trigger 1014, and the combined value of the LUTDMA_AUTOMODE_EN register 1008 and the MODE_SEL register 1010. Based on the input, the MUX 1012 may output a start trigger for the LUTDMA engine 802 (referred to hereafter as (“LUTDMA_Start_Trigger 1016”).
At 1206, during a LUTDMA configuration preparation stage, software associated with the LUTDMA engine 802 may configure CDs and CPs for each ROI of a frame. At 1208, the software associated with the LUTDMA engine 802 may trigger the LUTDMA engine 802. At 1210, hardware of the LUTDMA engine 802 may execute workloads for a zeroth ROI (ROI 0). For instance, the hardware of the LUTDMA engine 802 may execute a CD for the zeroth ROI and the hardware may update configurations related to the zeroth ROI. At 1212, a CP associated with the zeroth ROI may configure LUTDMA automode (e.g., LUTDMA_AUTOMODE_EN=1), which may cause the LUTDMA engine 802 to operate in automode as described above.
At 1214, the LUTDMA engine 802 may determine whether an indication of ROI START has been received. Upon positive determination, at 1216, the hardware of the LUTDMA engine 802 may transfer region of interest data associated with the zeroth ROI. At 1218, the hardware of the LUTDMA engine 802 may determine whether ROI_DONE_irq has been received. Upon negative determination, the hardware of the LUTDMA engine 802 may return to 1216. Upon positive determination, at 1220, the hardware of the LUTDMA engine 802 may determine whether a current ROI is a last ROI for a frame (e.g., based on a last CP associated with the current ROI). Upon positive determination, the LUTDMA engine 802 may return to 1206. Upon negative determination, at 1222, a LUTDMA start may be triggered (e.g., via a hardware based trigger) for a next ROI of the frame. At 1224, the hardware of the LUTDMA engine 802 may execute workloads for the next ROI. For instance, the hardware of the LUTDMA engine 802 may execute a CD for the next ROI and the hardware may update configurations related to the next ROI.
At 1226, the hardware of the LUTDMA engine 802 may determine whether a current ROI is a last ROI for the frame (e.g., based on a last CP associated with the current ROI). Upon negative determination, the LUTDMA engine 802 may return to 1214. Upon positive determination, at 1228, a last CP of the current ROI may override LUTDMA automode (e.g., LUTDMA_AUTOMODE_EN=0). The LUTDMA engine 802 may then return to 1206.
As described above, the technologies described herein may be associated with various advantages. First, the technologies described herein may provide for the ability to stack ROI configurations (e.g., all ROI configurations) for a frame by software at the beginning of the frame. Second, the technologies described herein may provide for the ability to auto-trigger a LUTDMA accelerator (e.g., the LUTDMA engine 802) multiple times in a single frame duration based on display timing. Third, the technologies described herein may provide for the ability to enter and exit automode for the LUTDMA dynamically based on a display frame boundary. Fourth, the technologies described herein may provide for the ability to deterministically trigger an ROI frame transfer within a start window.
As noted above, some systems for multiple partial frame updates may be impacted by configuration execution latencies and/or ISR latencies. Such latencies may prevent a multiple partial frame update from occurring when ROIs of a frame are within a threshold of one another. The LUTDMA engine 802 may be a faster engine than an AHB interface. The LUTDMA engine 802 may program ROI configurations faster than an AHB interface and thus the LUTDMA engine 802 may reduce configuration execution latency. The LUTDMA engine 802 may remove or mitigate ISR latency as the LUTDMA engine 802 prepares packets for ROIs at the beginning of a frame. Thus, the LUTDMA engine may not wait for ISR latency before the LUTDMA engine 802 configures a next ROI for the frame. Since the LUTDMA engine 802 may be able to reduce latency associated with a multiple partial frame update, the LUTDMA engine 802 may facilitate successful performance of multiple partial frame updates.
The second portion may also include 32 bits. The second portion may include an indication of a memory size (referred to hereafter as “MEM_SIZE 1510”). The MEM SIZE 1510 may be a memory size in double words (DWORDs) that describe how many command packets are to be fetched from DDR memory. The MEM SIZE 1510 may be bits [13:0] of the second portion. The second portion may include first reserved bits 1512. The first reserved bits 1512 may be bits [23:14] of the second portion. The second portion may include a last indication 1514. The last indication 1514 may indicate, from software to hardware, that all command descriptors for a next frame have been programmed. The last indication 1514 may be bit of the second portion. The second portion may include second reserved bits 1516. The second reserved bits 1516 may be bits [31:25] of the second portion.
In one aspect, software associated with the LUTDMA engine 802 may configure command descriptors via AHB register programming. Based on a command descriptor, hardware of the LUTDMA engine 802 may fetch command packets and OP codes from external DDR memory through an AXI. Hardware of the LUTDMA engine 802 may decode an OPCODE and command packets in order to update software registers across blocks associated with a frame.
The OP code packet 1504 may be 32 bits. The OP code packet 1504 may be present in DDR memory in the format depicted in the diagram 1500. The OP code packet 1504 may include an address 1518 of a hardware register. The address 1518 may be bits [19:0] of the OP code packet 1504. The OP code packet 1504 may include reserved bits 1520. The reserved bits 1520 may be bits [26:20] of the OP code packet 1504. The OP code packet 1504 may include an absolute/relative indication (referred to hereafter as “ABS/REL 1522”). The ABS/REL 1522 may indicate whether the address is a relative address or an absolute address. The ABS/REL 1522 may be bit [27] of the OP code packet 1504. The OP code packet 1504 may include an operation code (OPCODE) 1524. Details pertaining to the OPCODE 1524 are described in Table 2 below. The OPCODE 1524 may be bits [31:28] of the OP code packet 1504.
Referring to Table 2 above, REG_WRITE may be an OPCODE operation for a single register write address, where the address specifies a register address in a decode space and where data specifies content to be written into a hardware register. REG_MODIFY may be an OPCODE operation for modifying specific fields of a register through a mask value. REG_BLK_WRITE_SINGLE may be an OPCODE operation for writing into index based LUTs. REG_BLK_WRITE_INC may be an OPCODE operation for writing into direct addressed LUTs.
At 1810, the first display processor component 1802 may obtain a software-based indication that indicates to start an execution of command packets. At 1816, the first display processor component 1802 may execute, based on the obtained software-based indication at 1810, a first set of command packets associated with a first region of interest (ROI) of a frame that is to be updated. At 1822, the first display processor component 1802 may obtain a hardware-based indication that indicates that the first set of command packets associated with the first ROI of the frame has been executed. At 1824, the first display processor component 1802 may execute, based on the obtained hardware-based indication at 1822, a second set of command packets associated with a second ROI of the frame that is to be updated.
At 1805, the first display processor component 1802 may configure, prior to the execution of the first set of command packets at 1816, the first set of command packets and a first set of command descriptors for the first set of command packets. At 1806, the first display processor component 1802 may configure, prior to the execution of the second set of command packets at 1824, the second set of command packets and a second set of command descriptors for the second set of command packets. At 1808, the first display processor component 1802 may store, in a queue, the first set of command descriptors and the second set of command descriptors, where executing the first set of command packets at 1816 may include executing the first set of command packets based on the first set of command descriptors, and where executing the second set of command packets at 1824 may include executing the second set of command packets based on the second set of command descriptors.
At 1812, the first display processor component 1802 may retrieve, from memory, the first set of command packets based on the stored first set of command descriptors stored at 1808. At 1818, the first display processor component 1802 may retrieve, from the memory, the second set of command packets based on the stored second set of command descriptors stored at 1808.
In one aspect, a command packet in the second set of command packets may indicate that the second ROI is a last ROI for the frame, and at 1828, the first display processor component 1802 may execute, based on a second obtained software-based indication, a third set of command packets associated with an ROI of a second frame that is to be updated.
In one aspect, the first set of command packets includes a first operation code (OPCODE) and the second set of command packets includes a second OPCODE, and at 1814, the first display processor component 1802 may decode the first OPCODE, where configuring the first set of registers includes configuring the first set of registers based on the decoded first OPCODE. At 1820, the first display processor component 1802 may decode the second OPCODE, where configuring the second set of registers includes configuring the second set of registers based on the decoded second OPCODE.
At 1830, the first display processor component 1802 may obtain a second hardware-based indication that indicates that the second set of command packets associated with the second ROI of the frame has been executed. At 1832, the first display processor component 1802 may execute, based on the obtained second hardware-based indication at 1830, a third set of command packets associated with a third ROI of the frame that is to be updated.
At 1826, the first display processor component 1802 may output an indication of at least one of the executed first set of command packets or the executed second set of command packets. For instance, at 1826A, the first display processor component 1802 may transmit (e.g., to the second display processor component 1804) the indication of at least one of the executed first set of command packets or the executed second set of command packets.
At 1902, the apparatus obtains a software-based indication that indicates to start an execution of command packets. For example,
At 1904, the apparatus executes, based on the obtained software-based indication, a first set of command packets associated with a first region of interest (ROI) of a frame that is to be updated. For example,
At 1906, the apparatus obtains a hardware-based indication that indicates that the first set of command packets associated with the first ROI of the frame has been executed. For example,
At 1908, the apparatus executes, based on the obtained hardware-based indication, a second set of command packets associated with a second ROI of the frame that is to be updated. For example,
In one aspect, the first ROI of the frame and the second ROI of the frame may be associated with a partial frame update of the frame. In an example, a partial frame update may refer to pixel data associated with the first ROI being transferred to a frame buffer in a DDIC. For example, the aforementioned aspect may correspond to the partial frame update 502.
In one aspect, the first ROI of the frame may be within a threshold distance of the second ROI of the frame. For example, the first ROI 512 may be within a threshold distance of the second ROI 516 in
In one aspect, obtaining the hardware-based indication may include obtaining the hardware-based indication based on pixel data associated with the first ROI being removed from a buffer. For example, the aforementioned aspect may correspond to PP_DONE_irq 1006. In an example, the buffer may be or include the ping-pong buffers 1714.
In one aspect, obtaining the hardware-based indication may include obtaining the hardware-based indication based on a counter associated with the first ROI reaching a software programmable value. For example, the aforementioned aspect may correspond to WR_PTR_irq 1004. The counter may be based on pixel data being transferred.
In one aspect, the apparatus (e.g., a display processor) may configure, prior to the execution of the first set of command packets, the first set of command packets and a first set of command descriptors for the first set of command packets. For example,
In one aspect, the apparatus (e.g., a display processor) may configure, prior to the execution of the second set of command packets, the second set of command packets and a second set of command descriptors for the second set of command packets. For example,
In one aspect, the apparatus (e.g., a display processor) may store, in a queue, the first set of command descriptors and the second set of command descriptors, where executing the first set of command packets may include executing the first set of command packets based on the first set of command descriptors, and where executing the second set of command packets may include executing the second set of command packets based on the second set of command descriptors. For example,
In one aspect, the apparatus (e.g., a display processor) may retrieve, from memory, the first set of command packets based on the stored first set of command descriptors. For example,
In one aspect, the apparatus (e.g., a display processor) may retrieve, from the memory, the second set of command packets based on the stored second set of command descriptors. For example,
In one aspect, retrieving the first set of command packets from the memory may include retrieving the first set of command packets from the memory via an advanced extensible interface (AXI), and where retrieving the second set of command packets from the memory may include retrieving the second set of command packets from the memory via the AXI. For example, retrieving the first set of command packets from the memory at 1812 may include retrieving the first set of command packets from the memory via an advanced eXtensible interface (AXI), and where retrieving the second set of command packets from the memory at 1818 may include retrieving the second set of command packets from the memory via the AXI. In an example, the AXI may be or include the AXI 804.
In one aspect, the stored first set of command descriptors may include a first set of memory addresses and sizes of the first set of command packets and the stored second set of command descriptors may include a second set of memory addresses and sizes of the second set of command packets, where retrieving the first set of command packets based on the stored first set of command descriptors may include retrieving the first set of command packets based on the first set of memory addresses and sizes, and where retrieving the second set of command packets based on the stored second set of command descriptors may include retrieving the second set of command packets based on the second set of memory addresses and sizes. For example, the first set of memory addresses and sizes and the second set of memory addresses and sizes may be associated with the MEM_ADDR 1508 and the MEM_SIZE 1510. In an example, retrieving the first set of command packets based on the stored first set of command descriptors at 1812 may include retrieving the first set of command packets based on the first set of memory addresses and sizes, and where retrieving the second set of command packets based on the stored second set of command descriptors at 1818 may include retrieving the second set of command packets based on the second set of memory addresses and sizes.
In one aspect, a command packet in the second set of command packets may indicate that the second ROI is a last ROI for the frame, and the apparatus (e.g., a display processor) may execute, based on a second obtained software-based indication, a third set of command packets associated with an ROI of a second frame that is to be updated. For example,
In one aspect, the hardware-based indication may include an interrupt request (irq). For example, the hardware-based indication may be WR_PTR_irq 1004 or PP_DONE_irq 1006.
In one aspect, executing the first set of command packets may include configuring a first set of configuration registers for the first ROI, and where executing the second set of command packets may include configuring a second set of configuration registers for the second ROI. For example, executing the first set of command packets at 1816 may include configuring a first set of configuration registers for the first ROI, and executing the second set of command packets at 1824 may include configuring a second set of configuration registers for the second ROI.
In one aspect, the first set of command packets may include a first operation code (OPCODE) and the second set of command packets may include a second OPCODE, and the apparatus (e.g., a display processor) may decode the first OPCODE, where configuring the first set of configuration registers may include configuring the first set of configuration registers based on the decoded first OPCODE. For example,
In one aspect, the first set of command packets may include a first operation code (OPCODE) and the second set of command packets may include a second OPCODE, and the apparatus (e.g., a display processor) may decode the second OPCODE, where configuring the second set of configuration registers may include configuring the second set of configuration registers based on the decoded second OPCODE. For example,
In one aspect, the first OPCODE may include a first non-operation, a first register write operation, a first register modify operation, a first single block write operation, a first incremented block write operation, a first multiple block write operation, a first look-up table (LUT) operation, or a first reserved operation, and the second OPCODE may include a second non-operation, a second register write operation, a second register modify operation, a second single block write operation, a second incremented block write operation, a second multiple block write operation, a second look-up table (LUT) operation, or a second reserved operation. For example, the aforementioned aspect may pertain to Table 2 above.
In one aspect, executing the first set of command packets may include executing the first set of command packets via a configuration accelerator, and where executing the second set of command packets may include executing the second set of command packets via the configuration accelerator. For example, executing the first set of command packets at 1186 may include executing the first set of command packets via a look-up table direct memory access (LUTDMA) engine (i.e., a configuration accelerator), and executing the second set of command packets at 1824 may include executing the second set of command packets via the LUTDMA engine (i.e., a configuration accelerator). In an example, the configuration accelerator may be or include the LUTDMA engine 802.
In one aspect, the obtained software-based indication may be associated with a first latency, the obtained hardware-based indication may be associated with a second latency, and the first latency may be greater than the second latency. For example, the first latency may be or include the ISR latency 704 and/or the config execution latency 706. In another example, the aforementioned aspect may correspond to the example 1302 in
In one aspect, the apparatus (e.g., a display processor) may obtain a second hardware-based indication that indicates that the second set of command packets associated with the second ROI of the frame has been executed. For example,
In one aspect, the apparatus (e.g., a display processor) may execute, based on the obtained second hardware-based indication, a third set of command packets associated with a third ROI of the frame that is to be updated. For example,
In one aspect, the apparatus (e.g., a display processor) may output an indication of at least one of the executed first set of command packets or the executed second set of command packets. For example,
In one aspect, outputting the indication of at least one of the executed first set of command packets or the executed second set of command packets may include: transmitting the indication of at least one of the executed first set of command packets or the executed second set of command packets. For example,
In one aspect, outputting the indication of at least one of the executed first set of command packets or the executed second set of command packets may include storing the indication of at least one of the executed first set of command packets or the executed second set of command packets. For example, outputting the indication of at least one of the executed first set of command packets or the executed second set of command packets at 1826 may include storing the indication of at least one of the executed first set of command packets or the executed second set of command packets.
In configurations, a method or an apparatus for display processing is provided. The apparatus may be a DPU, a display processor, or some other processor that may perform display processing. In aspects, the apparatus may be the display processor 127 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus may include means for obtaining a software-based indication that indicates to start an execution of command packets. The apparatus may further include means for executing, based on the obtained software-based indication, a first set of command packets associated with a first region of interest (ROI) of a frame that is to be updated. The apparatus may further include means for obtaining a hardware-based indication that indicates that the first set of command packets associated with the first ROI of the frame has been executed. The apparatus may further include means for executing, based on the obtained hardware-based indication, a second set of command packets associated with a second ROI of the frame that is to be updated. The apparatus may further include means for configuring, prior to the execution of the first set of command packets, the first set of command packets and a first set of command descriptors for the first set of command packets. The apparatus may further include means for configuring, prior to the execution of the second set of command packets, the second set of command packets and a second set of command descriptors for the second set of command packets. The apparatus may further include means for storing, in a queue, the first set of command descriptors and the second set of command descriptors, where executing the first set of command packets includes executing the first set of command packets based on the first set of command descriptors, and where executing the second set of command packets includes executing the second set of command packets based on the second set of command descriptors. The apparatus may further include means for retrieving, from memory, the first set of command packets based on the stored first set of command descriptors. The apparatus may further include means for retrieving, from the memory, the second set of command packets based on the stored second set of command descriptors. The apparatus may further include means for executing, based on a second obtained software-based indication, a third set of command packets associated with an ROI of a second frame that is to be updated. The apparatus may further include means for decoding the first OPCODE, where configuring the first set of configuration registers includes configuring the first set of configuration registers based on the decoded first OPCODE. The apparatus may further include means for decoding the second OPCODE, where configuring the second set of configuration registers includes configuring the second set of configuration registers based on the decoded second OPCODE. The apparatus may further include means for obtaining a second hardware-based indication that indicates that the second set of command packets associated with the second ROI of the frame has been executed. The apparatus may further include means for executing, based on the obtained second hardware-based indication, a third set of command packets associated with a third ROI of the frame that is to be updated. The apparatus may further include means for outputting an indication of at least one of the executed first set of command packets or the executed second set of command packets.
It is understood that the specific order or hierarchy of blocks/steps in the processes, flowcharts, and/or call flow diagrams disclosed herein is an illustration of example approaches. Based upon design preferences, it is understood that the specific order or hierarchy of the blocks/steps in the processes, flowcharts, and/or call flow diagrams may be rearranged. Further, some blocks/steps may be combined and/or omitted. Other blocks/steps may also be added. The accompanying method claims present elements of the various blocks/steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language of the claims, where reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.
Unless specifically stated otherwise, the term “some” refers to one or more and the term “or” may be interpreted as “and/or” where context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. The words “module,” “mechanism,” “element,” “device,” and the like may not be a substitute for the word “means.” As such, no claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.” Unless stated otherwise, the phrase “a processor” may refer to “any of one or more processors” (e.g., one processor of one or more processors, a number (greater than one) of processors in the one or more processors, or all of the one or more processors) and the phrase “a memory” may refer to “any of one or more memories” (e.g., one memory of one or more memories, a number (greater than one) of memories in the one or more memories, or all of the one or more memories).
In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term “processing unit” has been used throughout this disclosure, such processing units may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique described herein, or other module is implemented in software, the function, processing unit, technique described herein, or other module may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to: (1) tangible computer-readable storage media, which is non-transitory; or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and/or data structures for implementation of the techniques described in this disclosure. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, compact disc-read only memory (CD-ROM), or other optical disk storage, magnetic disk storage, or other magnetic storage devices. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks usually reproduce data magnetically, while discs usually reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.
The techniques of this disclosure may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs, e.g., a chip set. Various components, modules or units are described in this disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need realization by different hardware units. Rather, as described above, various units may be combined in any hardware unit or provided by a collection of inter-operative hardware units, including one or more processors as described above, in conjunction with suitable software and/or firmware. Accordingly, the term “processor,” as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques may be fully implemented in one or more circuits or logic elements.
The following aspects are illustrative only and may be combined with other aspects or teachings described herein, without limitation.
Various aspects have been described herein. These and other aspects are within the scope of the following claims.
