Efficient parallel cyclic redundancy check calculation using a novel table lookup approach

Abstract

A system for cyclic redundancy check (CRC) calculations with modulo-2 multiplication is disclosed for repetitive CRC computations that optimizes processing efficiency and maximizes capacity. The resulting system results in the use of relatively fewer logical gates and conserves on power. The system receives a message ({right arrow over (m)}) including a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (β)}i). The system performs a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}) using the relationship given by:

Description

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts:

FIG. 1 illustrates a simplified block diagram of an exemplary digital signal processing system and controller for cyclic redundancy check calculations according to one embodiment of the present disclosure; and

FIG. 2 is a simplified flowchart illustrating a method in accordance with one embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 and 2, discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only, and should not be construed in any way to limit the scope of the disclosure. Hereinafter, certain aspects of the present disclosure are described in relation to illustrative embodiments and operations of wireless communications systems and networks. Those skilled in the art, however, will understand that the principles and teachings of the present disclosure may be implemented in a variety of suitably arranged signal processing systems utilized in any number of end-equipment applications.

Typical Galois multiply-accumulate systems include a message ({right arrow over (m)}) consisting of N bits. The message is a superposition of a plurality of blocks ({right arrow over (b)}_i). Each block ({right arrow over (b)}_i) is of a fixed size (e.g., M bits). The blocks are multiplied over a Galois Field of prime two (e.g., GF(2)) with unit vectors ({right arrow over (e)}_i) shifted by M bits with respect to each other. Thus, the message ({right arrow over (m)}) can be decomposed as shown by Equation 1 below:

$\begin{array}{cc}\overrightarrow{m}=\sum _{i=0}^{N/M-1}{\overrightarrow{b}}_i\otimes {\overrightarrow{e}}_i& \left[\mathrm{Eqn}.1\right]\end{array}$

The summation and the multiplication operations included in Equation 1 are performed over GF(2). The GF(2) multiplication is shown as the symbol while the GF(2) addition operation (an XOR operation) is shown as the symbol “⊕”.

As an example of a typical application for Galois multiply-accumulate system, suppose a message ({right arrow over (m)}) containing sixteen bits (N=16) requires decomposition and is equal to the binary sequence [1101111100111010]. Suppose further that message ({right arrow over (m)}) is a superposition of blocks ({right arrow over (b)}_i) of a fixed number of bits (M). For example, suppose M=4 and is equal to the polynomial degree (or CRC width) W=3. Finally, suppose that the CRC polynomial ({right arrow over (p)}) is equal to [1010].

In a typical Galois application, message ({right arrow over (m)}) is first divided into four blocks [{right arrow over (b)}₃ {right arrow over (b)}₂ {right arrow over (b)}₁ {right arrow over (b)}₀] of four bits each, where {right arrow over (b)}₀=1010, {right arrow over (b)}₁=0011, {right arrow over (b)}₂=1111 and {right arrow over (b)}₃=1101. Moreover, message ({right arrow over (m)}) is the superposition of the blocks ({right arrow over (b)}_i) multiplied by unit vectors ({right arrow over (e)}_i) as given in Equation 2 below:

{right arrow over (m)}={right arrow over (b)}₀{right arrow over (e)}₀⊕{right arrow over (b)}₁{right arrow over (e)}₁⊕{right arrow over (b)}₂{right arrow over (e)}₂⊕{right arrow over (b)}₃{right arrow over (e)}₃.   [Eqn. 2]

Continuing with the example above, suppose that the unit vectors ({right arrow over (e)}_i) are given by {right arrow over (e)}₀=1, {right arrow over (e)}₁=10000, {right arrow over (e)}₂=100000000 and {right arrow over (e)}₃=1000000000000. Next, the CRC of the message ({right arrow over (m)}) is given by the modulo-2 division of message ({right arrow over (m)}) by the CRC polynomial ({right arrow over (p)}) as given in Equation 3 below:

$\begin{array}{cc}\mathrm{CRC}\left(\overrightarrow{m}\right)\equiv \mathrm{CRC}\left(\sum _i{\overrightarrow{b}}_i\otimes {\overrightarrow{e}}_i\right)=\sum _i\mathrm{CRC}\left({\overrightarrow{b}}_i\otimes \left({\overrightarrow{e}}_i\right)\right).& \left[\mathrm{Eqn}.3\right]\end{array}$

Using the modulation properties of Equations 4 and 5 below and after assuming that x is smaller than p (i.e., mod(x)_p=x), Equation 3 may be simplified to Equation 6 below, where {right arrow over (β)}_i≡CRC({right arrow over (e)}_i) and {right arrow over (β)}_i is a set of pre-computed coefficients:

$\begin{array}{cc}{\mathrm{mod}\left(x\oplus y\right)}_p={\mathrm{mod}\left(x\right)}_p\oplus {\mathrm{mod}\left(y\right)}_p;& \left[\mathrm{Eqn}.4\right]\\ {\mathrm{mod}\left(x\otimes y\right)}_p={\mathrm{mod}\left({\mathrm{mod}\left(x\right)}_p\otimes {\mathrm{mod}\left(y\right)}_p\right)}_p;& \left[\mathrm{Eqn}.5\right]\\ \mathrm{CRC}\left(\overrightarrow{m}\right)\equiv \sum _i\mathrm{CRC}\left({\overrightarrow{b}}_i\otimes {\overrightarrow{\beta }}_i\right).& \left[\mathrm{Eqn}.6\right]\end{array}$

Finally, Equation 6 simplifies to Equation 7 below, where the CRC calculation essentially becomes a series of Galois multiply-accumulate operations:

$\begin{array}{cc}\mathrm{CRC}\left(\overrightarrow{m}\right)\equiv \sum _i\mathrm{gmpy}\left({\overrightarrow{b}}_i,{\overrightarrow{\beta }}_i\right).& \left[\mathrm{Eqn}.7\right]\end{array}$

In Equation 7, the blocks ({right arrow over (b)}_i) are of a particular size (e.g., W bits or less).

FIG. 1 a simplified block diagram of a system 100 for cyclic redundancy check calculations with modulo-2 multiplication in accordance with one embodiment of the present disclosure. System 100 includes a digital signal processing system 101 having an input 102 and an output 103. By way of example, system 100 may include wire line or wireless communication devices (including cell phones, PCS handsets, personal digital assistant (PDA) handsets, portable computers, telemetry devices, etc.), computer systems, audio and video equipment, satellite communications, multimedia applications, home automation systems and any other systems requiring digital signal processing. Digital signal processing system 101 includes a controller 104 for performing cyclic redundancy check calculations according to one embodiment of the present disclosure. Digital signal processing system 101 may optionally include a lookup table 106. It should be understood that embodiments of the present disclosure may implemented into existing equipment, such as multipliers.

In accordance with one embodiment of the present disclosure, however, a series of modolu-2 multiply-accumulate operations is preferable. In alternate embodiments, modulo-2 multiplications may be used for at least some of the repetitive operations performed in the cyclic redundancy check (CRC) computations. As explained in greater detail below, a series of N-bit messages is parsed into blocks of size M for N/M parallel modulo-2 and multiply-accumulate operations. Finally, the accumulator is divided by the polynomial ({right arrow over (p)}).

As a specific example, Equation 3 above may be expanded using Equation 8 to arrive at Equation 9 below.

$\begin{array}{cc}{\mathrm{mod}\left(x\otimes y\right)}_p={\mathrm{mod}\left({\mathrm{mod}\left(x\right)}_p\otimes {\mathrm{mod}\left(y\right)}_p\right)}_p& \left[\mathrm{Eqn}.8\right]\\ \begin{array}{c}\mathrm{CRC}\left(\overrightarrow{m}\right)=\sum _i\mathrm{CRC}\left({\overrightarrow{b}}_i\otimes \left({\overrightarrow{e}}_i\right)\right)\\ =\mathrm{CRC}(\sum _i\mathrm{CRC}\left({\overrightarrow{b}}_i\text{)}\otimes {\overrightarrow{\beta }}_i\right)\end{array}& \left[\mathrm{Eqn}.9\right]\end{array}$

Assuming that the block sizes ({right arrow over (b)}_i) are of size W bits or less, Equation 9 may be further simplified to a series of modolu-2 multiply-accumulate operations, as shown in Equation 10:

$\begin{array}{cc}\mathrm{CRC}\left(\overrightarrow{m}\right)\equiv \mathrm{CRC}\left(\sum _i{\overrightarrow{b}}_i\otimes {\overrightarrow{\beta }}_i\right)& \left[\mathrm{Eqn}.10\right]\end{array}$

The division operation by the CRC polynomial is an epilog operation. Therefore, processing speed becomes less essential and reconfigurability becomes the main consideration.

FIG. 2 is a simplified flowchart illustrating method 200. Method 200 provides a method for cyclic redundancy check (CRC) operations in accordance with one embodiment of the present disclosure. Method 200 begins with receiving a message ({right arrow over (m)}) from, for example, input 102 of system 100 in step 201. The message includes a plurality of blocks ({right arrow over (b)}_i) and a set of pre-computed coefficients ({right arrow over (β)}_i) In step 202, controller 104 performs a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}) using the relationship given by Equation 10 above. Method 200 finally ends with step 203 by outputting a signal from digital signal processing system 101.

Embodiments of the present disclosure offer a number of advantages over previously known systems and methods. For example, the present disclosure is based on modulo-2 multiplications and therefore uses relatively few logical gates and consumes less power when compared to prior art Galois multiplication techniques. Moreover, because the modulo-2 multiplication is not followed by a division, the operation may be performed at higher clock speed than the prior art systems based on Galois multiplications.

Conventional Galois multiplication methods depend upon the polynomials involved in the operation. As noted above, Galois multipliers have hardwired CRC polynomials and therefore are not reconfigurable to support other polynomials. Embodiments of the modulo-2 multiplication operation in accordance with the present disclosure, however, do not depend on a specific polynomial. Moreover, a lookup table approach may be implemented for full reconfigurability during polynomial division using, for example, lookup table 106. Thus, the polynomial value may be customized to suit a particular application.

Previous systems and methods require N/W CRC operations. According to one embodiment of the present disclosure, however, a series of GF(2) multiplications requires only one final CRC operation. Thus, one embodiment of the present disclosure saves at least (N/W)-1 unnecessary divisions.

Existing systems may be modified by turning off the carry bit capability and using the modulo-2 multiplication in accordance with the present disclosure. As another example, in one embodiment according to the present disclosure, the system and method may include performing the division of the accumulator by the CRC polynomial by a nibble using lookup table 106. Lookup table 106 is preferably made up of 16×W bits.

Although certain aspects of the present disclosure have been described in relation to specific systems, standards and structures, it should be easily appreciated by one skilled in the art that embodiments of the system of the present disclosure provides and comprehends a wide array of variations and combinations easily adapted to a number of signal processing systems. As described herein, the relative arrangement and operation of necessary functions may be provided in any manner suitable for a particular application. All such variations and modifications are hereby comprehended. It should also be appreciated that the constituent members or components of this system may be produced or provided using any suitable hardware, firmware, software, or combination(s) thereof.

The embodiments and examples set forth herein are therefore presented to best explain the present disclosure and its practical application, and to thereby enable those skilled in the art to make and utilize the system of the present disclosure. The description as set forth herein is therefore not intended to be exhaustive or to limit any invention to a precise form disclosed. As stated throughout, many modifications and variations are possible in light of the above teaching without departing from the spirit and scope of the following claims.

Claims

1. A method for cyclic redundancy checks (CRC), comprising: receiving a message ({right arrow over (m)}), wherein the message comprises a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (β)}i); andperforming a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}), wherein the operation is given by:

2. The method of claim 1, wherein the coefficients ({right arrow over (β)}i) are a function of a unit vector ({right arrow over (e)}i).

3. The method of claim 2, wherein the coefficients ({right arrow over (β)}i) are given by: {right arrow over (β)}i≡CRC({right arrow over (e)}i).

4. The method of claim 1, wherein the blocks ({right arrow over (b)}i) are of a fixed number of bits (W).

5. The method of claim 4 further comprising: reconfiguring a CRC polynomial using a lookup table.

6. The method of claim 5, wherein the lookup table is made of 16×W bits.

7. The method of claim 5, wherein reconfiguring the CRC polynomial is accomplished by loading a new lookup table.

8. A system for cyclic redundancy checks (CRC), comprising: a controller capable of:receiving a message ({right arrow over (m)}), wherein the message comprises a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (β)}i); andperforming a modulo-2 multiply-accumulate operation on the message ({right arrow over (m)}), wherein the operation is given by:

9. The system of claim 8, wherein the coefficients ({right arrow over (β)}i) are a function of a unit vector ({right arrow over (e)}i)

10. The system of claim 9, wherein the coefficients ({right arrow over (β)}i) are given by: {right arrow over (β)}i≡CRC({right arrow over (e)}i).

11. The system of claim 8, wherein the blocks ({right arrow over (b)}i) are of a fixed number of bits (W).

12. The system of claim 11 further comprising: a lookup table to aid in reconfiguring a CRC polynomial.

13. The system of claim 12, wherein the lookup table is made of 16×W bits.

14. The system of claim 12, wherein the reconfiguring of the CRC polynomial is accomplished by loading a new lookup table.

15. For use in a signal processing system, a process for cyclic redundancy checks (CRC), comprising: receiving a message ({right arrow over (m)}), wherein the message comprises a plurality of blocks ({right arrow over (b)}i) and a set of pre-computed coefficients ({right arrow over (β)}i); andperforming modulo-2 multiply-accumulate operations on the message ({right arrow over (m)}).

16. The process of claim 15, wherein the operations are given by:

17. The process of claim 15, wherein the coefficients ({right arrow over (β)}i) are a function of a unit vector ({right arrow over (e)}i).

18. The process of claim 17, wherein the coefficients ({right arrow over (β)}i) are given by: {right arrow over (β)}i≡CRC({right arrow over (e)}i).

19. The process of claim 15, wherein the blocks ({right arrow over (b)}i) are of a fixed number of bits (W).

20. The process of claim 19 further comprising: reconfiguring a CRC polynomial using a lookup table.

21. The process of claim 20, wherein the lookup table is made of 16×W bits.

22. The process of claim 20, wherein reconfiguring the CRC polynomial is accomplished by loading a new lookup table.