Patent Application
20090009430
The present invention relates to recovery of electric energy accumulated in a capacitance and, more particularly, to an apparatus which recovers electric charges accumulated by applying a pulsed voltage to a capacitor formed on a cell constituting a screen of a plasma panel display (PDP), a plasma display panel, and an electric charging/discharging method.
There is known a technique for recovering electric energy of an applied pulse such that electric charges accumulated by applying a sustain pulse voltage to a capacitor formed in a plurality of cells constituting a screen of a PDP are recovered by using a capacitor for recovering electric energy. The recovered electric charges are used to apply a next sustain pulse voltage. In this technique, electric charges accumulated in a cell at a rising edge of one applied pulse are recovered at a trailing edge of the applied pulse.
Japanese Patent Publication Laid-Open No. 10-105114 (A) disclosed on Apr. 24, 1998 describes a power recovery apparatus for a PDP which enables charging and discharging power also in application of a negative voltage. This power recovery apparatus includes a positive voltage charging/discharging unit which charges a positive voltage and discharges the charged positive voltage to a discharging electrode in a next electrode discharging state, a negative voltage discharging unit which charges a negative voltage and discharges the charged negative voltage to the discharging electrode in a next electrode discharging state, and a controller which controls inputting of an external voltage and electric charging/discharging by the positive/negative voltage charging/discharging unit.
Patent Document 1: Japanese Patent Publication Laid-Open No. 10-105114
International Patent Publication Laid-Open No. WO 00/00956 (A) published on Jan. 6, 2000 discloses a method and apparatus for generating a control signal which can variably determine a switching timing of a power recovery circuit of a plasma display panel television. A variable range pulse generating unit generates a variable range pulse which determines an allowable maximum variable range of recovery power providing timing, and a first counter is enabled by the variable range pulse, counts clock signals, and periodically outputs a count value. A second counter and a third counter count the numbers of times of switching between a first switch and a second switch to set a first reference value and a second reference value, respectively. A rising pulse generating unit periodically compares the count value with the first reference value. When the count value and the first reference value are equal to each other, a logical level of an output signal is inverted from low to high. A falling pulse generating unit periodically compares the count value with the second reference value. When the count value and the second reference value are equal to each other, the logical level of the output signal is inverted from high to low. An AND gate calculates a logical product between output signals from the rising pulse generating unit and the falling pulse generating unit to generate a control signal. A pulse duration of the control signal is determined by the first reference value and the second reference value. The two reference values can be externally and variably determined.
Patent Document 2: WO 00/00956
In a PDP, as a pulse waveform applied to an electrode for causing discharging in a cell, a sustain pulse having an asymmetrical waveform are occasionally used. In this case, with a normal power recovery circuit, a potential of a capacitor for power recovery gradually shifts in one polar direction, or a power applied to a display electrode capacitor cannot be sufficiently recovered.
The present inventors recognize that it is desirable to realize a circuit which can sufficiently recover supplied electric energy even though a periodic pulsed voltage having an arbitrary waveform including an asymmetric waveform is applied to an electrode for display.
It is an object of the present invention to realize a circuit which can sufficiently recover electric energy supplied to a capacitance by a periodic pulsed voltage having an arbitrary waveform.
According to a characteristic feature of the present invention, a charging/discharging apparatus which charges a capacitance to be charged/discharged by applying a voltage includes: a recovery capacitor for recovering electric energy which has one terminal connected to a first power supply through first switch means and another terminal connected to a second power supply through second switch means; first path forming means which has one terminal connected to a connection point between the second power supply and the other terminal of the recovery capacitor and another terminal connected to the capacitance to be charged/discharged, and charges the capacitance to be charged/discharged through a resonant inductor when the first switch means is turned on; second path forming means which has one terminal connected to a connection point between the first power supply and the one terminal of the recovery capacitor and another terminal connected to the capacitance to be charged/discharged, and discharges the capacitance to be charged/discharged through the resonant inductor when the second switch means is turned on to recover electric energy in the recovery capacitor; and control means which controls the first and second switch means and the first and second path forming means.
The present invention also relates to an electric charging/discharging method for realizing functions of the apparatus.
According to the present invention, electric energy supplied to a capacitance by applying a pulsed voltage having an arbitrary waveform can be sufficiently recovered.
An embodiment of the present invention will be described below with reference to the accompanying drawings. Identical reference numerals denote similar constituent elements in the drawings.
In the PDP 10, display electrodes X and Y constituting an electrode pair for causing display discharging are arranged in parallel to each other, and an address electrode A is arranged orthogonally to the display electrodes X and Y. The display electrode X is a sustain (sustainment) electrode, and the display electrode Y is a scan (scanning) electrode. The display electrodes X and Y typically extend in a row direction or a horizontal direction of the screen, and the address electrode A extends in a column direction or a vertical direction.
The drive unit 50 includes a driver control circuit 51, a data conversion circuit 52, a power supply circuit 53, an X electrode driver circuit or an X driver circuit 61, a Y electrode driver circuit or a Y driver circuit 64, and an address electrode driver circuit or an A driver circuit 68. Depending on conditions, the drive unit 50 is packaged as a configuration of an integrated circuit which can include a ROM. Field data Df representing emission intensities of three primary colors R, G, and B are input from an external device such as a TV tuner or a computer to the drive unit 50 together with various synchronous signals. The field data Df is temporarily stored in a field memory in the data conversion circuit 52. The data conversion circuit 52 converts the field data Df into sub-field data Dsf for grayscale display to supply the sub-field data Dsf to the A driver circuit 68. The sub-field data Dsf is a set of 1-bit display data per cell. A value of each bit thereof represents whether or not light emission of each cell is necessary in a corresponding sub-field SF.
The X driver circuit 61 includes a reset circuit 62 which applies a voltage to initializing the display electrode X to equalize wall voltages of a plurality of cells constituting the PDP display screen and a sustain circuit 63 which applies a sustain pulse to the display electrode X to cause the cells to perform display discharging. The Y driver circuit 64 includes a reset circuit 65 which applies an initializing voltage to the display electrode Y, a scan circuit 66 which applies a scan pulse to the display electrode Y in addressing, and a sustain circuit 67 which applies a sustain pulse to the display electrode Y to cause the cells to perform display discharging. The A driver circuit 68 applies an address pulse to the address electrode A designated by the sub-field data Dsf depending on display data.
The driver control circuit 51 controls application of a pulse voltage and transfer of the sub-field data Dsf. The power supply circuit 53 supplies a drive power to a required portion in the unit. The driver control circuit 51 may take information representing on cells and off cells obtained by the sub-field data Dsf from the data conversion circuit 52, may determine the display electrodes X and Y related to the on cells and the off cells, and may supply data related to the display electrodes X and Y related to the off cells to the sustain circuits 63 and 67.
One picture (screen) is typically constituted by one frame period, one frame is constituted by two fields in interlace type scanning, and one frame is constituted by one field in progressive type scanning. In display by the PDP 10, in order to achieve color reproduction by binary light-emitting control, one field F of time series of an input image in such a field period is typically divided into a predetermined number (q) of sub-fields SF. Typically, each field F is replaced with a set of q sub-fields SF. Frequently, different weights 20, 21, 22, . . . , 2q-1 and the like are sequentially given to the sub-fields SF, respectively, and the number of times of display discharging of each sub-field SF. Depending on combinations of (light-emitting state)/(non-light-emitting state) in sub-field units, a luminance setting of N (=1+21+22+ . . . +2q-1) steps can be performed to each of the colors R, G, and B. In accordance with the field configuration, a field period Tf serving as a field transfer cycle is divided into q sub-field periods Tsf, and one sub-field period Tsf can be allocated to each of the sub-fields SF. Furthermore, the sub-field period Tsf is divided into a reset period TR for initialization, an address period TA for addressing, and a display period TS for light emission. Typically, the reset period TR and the address period TA have constant lengths regardless of their weights. However, the number of pulses in the display period TS is in proportion to the weight, and the length of the display period TS is in proportion to the weight. In this case, the length of the sub-field period Tsf is in proportion to the weight of the corresponding sub-field SF.
An order of the reset period TR, the address period TA, and the sustain period TS is not changed in the q sub-fields SF, and a drive sequence is repeated every sub-field SF. In the reset period TR of each sub-field SF, a negative pulse Prx1 and a positive pulse Prx2 are sequentially applied to all the display electrodes X, and a positive pulse Pry and a negative pulse Pry2 are sequentially applied to all the display electrodes Y. The pulses Prx1, Pry1, and Pry2 are ramp waveforms or obtuse waveform pulses the amplitudes of which gradually increase at a change rate of causing minute discharging. The pulses Prx1 and Pry1 which are applied at the beginning are applied to all the cells regardless of (light-emitting state)/(non-light-emitting state) in the sub-fields SF to generate appropriate wall voltages having the same polarity in all the cells. The pulses Prx2 and Pry2 are applied to cells in which appropriate wall charges are present to enable adjusting the wall voltages to a value corresponding to a differences between a discharge start voltage and a pulse amplitude. A drive voltage applied to the cell is a composite voltage representing a difference between amplitudes of the pulses applied to the display electrodes X and Y.
In the address period TA, wall charges required to maintain light emission are formed in only a cell to emit light. When all the display electrodes X and all the display electrodes Y are biased to predetermined potentials, a negative scan pulse −Vy is applied to the display electrode Y corresponding to a selected row every row selecting period (scanning time of one row). Moment that the row is selected, an address pulse Va is applied to only an address electrode A corresponding to a selected cell to cause address discharge. More specifically, potentials of address electrodes A1 to Am are binarily controlled based on the sub-field data Dsf of m columns of a selected row j. In the selected cell, discharging occurs between the display electrode Y and the address electrode A. The address discharging serves as a trigger to cause surface discharging between the display electrodes X and Y.
In the display period TS, a sustain pulse Ps having a predetermined polarity (positive polarity in the example in
In
In
Referring to
When the switch SW2 is turned on at the start of the rising period of the pulse P, a free-wheeling current flows from the capacitor C to the recovery capacitor Cr through the switch SW2 and the resonant inductor L, the electric charges q to CV are additionally accumulated in the power recovery capacitor Cr, the voltage of the capacitor C falls, and a falling edge of the pulse P is formed. When the voltage of the capacitor C almost reaches a negative peak voltage, the switch SW5 is turned on. The peak voltage is slightly higher than a ground potential of 0 V. In the falling period, a ground point GND of the clump circuit 14 clamps the voltage of the capacitor C to the ground potential of 0 V and maintains the voltage of the capacitor C at the ground potential of 0 V. Because of the diode D2, a current does not flows in an opposite direction of the free-wheeling current. Therefore, the switch SW2 is turned off at an arbitrary timing until the turn-off timing of the switch SW5 after the voltage reaches the peak voltage. Thereafter, the switch SW5 is turned off.
In this manner, electric charges, i.e., most of power supplied from the capacitor Cr to the capacitor C is recovered. The clump circuit 14 compensates for the voltage of the capacitor C to make the voltage equal to the predetermined voltage V. As described above, when the waveforms of the pulse P at the rising edge and the falling edge are symmetrical, power supplied to the capacitor C is sufficiently recovered.
In the power recovery circuit 12 in
Most of the electric charges supplied from the capacitor Cr at the rising edge of the pulse are desirably recovered by the capacitor Cr.
The pulse power supply and recovery circuits 110 and 120 in
The pulse power supply and recovery circuit 110 includes a power recovery capacitor Cr1 having one terminal connected to a ground point GND through the switch SW11 and the other terminal connected to a constant voltage source Vs+Vo through the switch SW12, a diode D11 having an anode (positive pole) connected to a connection point between one terminal of the capacitor Cr1 and the switch SW12 through the switch SW13, a diode D12 having an anode connected to a connection point between the other terminal of the capacitor Cr1 and the switch SW11 through the switch SW14, and a resonant inductor L1 having one terminal connected to a connection point between the cathodes (negative poles) of the diodes D11 and D12 and the other terminal connected to one display electrodes (X or Y) of one or two or more pairs of display electrodes X and Y of the capacitor Cp.
The pulse power supply and recovery circuit 120 includes a power recovery capacitor Cr2 having one terminal connected to the constant voltage source Vs through the switch SW21 and the other terminal connected to the ground point GND through the switch SW22, a diode D21 having a cathode connected to a connection point between one terminal of the recovery capacitor Cr2 and the switch SW22 through the switch SW23, a diode D22 having a cathode connected to a connection point between the other terminal of the recovery capacitor Cr2 and the switch SW21 through the switch SW24, and a resonant inductor L2 having one terminal connected to a connection point between the diode D21 and the diode D22 and the other terminal connected to one terminals of one or two or more pairs of display electrodes X and Y of the capacitor Cp.
The pulse power supply and recovery circuit 130 includes a power recovery capacitor Cr13 having one terminal connected to the constant voltage source Vs+Vo through the switch SW31 and the other terminal connected to the constant voltage source Vs through the switch SW22, a diode D31 having a cathode connected to a connection point between one terminal of the capacitor Cr3 and the switch SW32 through the switch SW33, a diode D32 having a cathode connected to a connection point between the other terminal of the capacitor Cr3 and the switch SW31 through the switch SW34, and a resonant inductor L3 having one terminal connected to a connection point between the anodes of the diodes D31 and D32 and the other terminal connected to one display electrodes of the pairs of display electrodes X and Y of the capacitor Cp.
The clamp circuit 140 includes a constant voltage source having a predetermined voltage Vs+Vo and connected to a connection point between a connection point between the resonant inductors L1, L2, and L3 and one display electrodes of the resonant inductors through the switch SW41, a constant voltage source having a predetermined voltage Vs and connected to the connection point through the switch SW42, and a ground point GND connected to the connection point through the switch SW45.
An operation will be described below. In the pulse power supply and recovery circuit 12 in
In the rising period PR of the pulse P1, when the switches SW11 and SW13 are turned on according to the control signals CSW11 and CSW13 from the control signal generating circuit 604, a current flows from the capacitor Cr1 to the display electrode capacitor Cp through the switch SW13, the diode D11, and the resonant inductor L1 which constitute a path 1, and a voltage between both the terminals of the capacitor Cr1 slightly decreases to form a rising edge of the pulse P1. When the voltage of the capacitor Cp reaches a peak potential Vp1, the switch SW41 of the clamp circuit 140 is turned on according to the control signal CSW41. Because of the diode D11, a current does not flow in a direction opposite to a direction of the supply current. Therefore, the switches SW11 and SW13 are turned off at an arbitrary timing until a turn-off timing of the switch SW41 after the voltage reaches the peak voltage. The peak potential Vp1 is slightly lower than Vs+Vo. In the rising period PR, electric charges q to Cr1 (Vs+Vo)/2, i.e. power, are supplied from the capacitor Cr1 to the capacitor Cp. In the clamp period PCL1, the voltage source Vs+Vo of the clamp circuit 140 clamps the voltage of the capacitor Cp to the voltage Vs+Vo, and maintains the display electrode capacitor Cp at the potential Vs+Vo. Thereafter, the switch SW41 is turned off according to the control signal CSW41. In the first falling period PF1 of the pulse P1, the switch SW42 is turned on according to the control signal CSW42, and the pulse P1, i.e., the voltage of the capacitor Cp, falls to the voltage Vs. In the subsequent final falling period PF2 of the pulse P1, the pulse P1, i.e., the voltage of the capacitor Cp, falls to the ground potential GND.
In the rising period PR of the pulse P2, when the switches SW12 and SW14 are turned on according to the control signals CSW12 and CSW14 from the control signal generating circuit 604, a current flows from the capacitor Cr1 to the display electrode capacitor Cp through the switch SW14, the diode D12, and the resonant inductor L1 which constitute a path 2, a voltage between both the terminals of the capacitor Cr1 slightly increases, and a rising edge of the pulse P2 is formed. When the voltage of the capacitor Cp reaches a peak potential Vp1, the switch SW41 of the clamp circuit 140 is turned on according to the control signal CSW41. Because of the diode D12, a current does not flow in a direction opposite to a direction of the supply current. Therefore, the switches SW12 and SW14 are turned off at an arbitrary timing until a turn-off timing of the switch SW41 after the voltage reaches the peak voltage. In the rising period RP, electric charges q to Cr1 (Vs+Vo)/2, i.e. power, are recovered from the capacitor Cp to the capacitor Cr1. In the clamp period PCL1, the voltage source Vs+Vo of the clamp circuit 140 clamps the voltage of the capacitor Cp to the voltage Vs+Vo and maintains the display electrode capacitor Cp at the potential Vs+Vo. Thereafter, the switch SW41 is turned off according to the control signal Csw41. In the first falling period PF1 of the pulse P2, the switch SW42 is turned on according to the control signal CSW42, and the pulse P2, i.e., the voltage of the capacitor Cp falls to the voltage Vs. In the subsequent final falling period PF2 of the pulse P2, the pulse P1, i.e., the voltage of the capacitor Cp falls to the ground potential GND.
In the final falling period PF2 to the ground potential GND of the pulse P1, when the switches SW21 and SW23 are turned on according to the control signals CSW21 and CSW23, a current flows from the display electrode capacitor Cp to the display electrode capacitor Cr2 through the switch SW23, the diode D21, and the resonant inductor L2 which constitute a path 1, a voltage between both the terminals of the capacitor Cr2 slightly decreases, and a final falling edge of the pulse P1 is formed. When the voltage of the capacitor Cp reaches a peak potential Vp3, the switch SW45 of the clamp circuit 140 is turned on according to the control signal CSW45. Because of the diode D21, a current does not flow in a direction opposite to a direction of the supply current. Therefore, the switches SW21 and SW23 are turned off at an arbitrary timing until a turn-off timing of the switch SW45 after the voltage reaches the peak voltage. The peak voltage Vp3 is slightly higher than the potential GND. In the falling period PF2, electric charges q to Cr2VS/2, i.e. power, are supplied from the capacitor Cr2 to the capacitor Cp. In the clamp period PCL2, the ground potential GND of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential GND (0 V) and maintains the display electrode capacitor Cp at the ground potential GND. Thereafter, the switch SW45 is turned off according to the control signal CSW45.
In the final falling period PF2 to the ground potential GND of the pulse P2, when the switches SW22 and SW24 are turned on according to the control signals CSW22 and CSW24, a current flows from the display electrode capacitor Cp to the display electrode capacitor Cr2 through the switch SW24, the diode D22, and the resonant inductor L2 which constitute a path 2, a voltage between both the terminals of the capacitor Cr slightly increases, and a falling edge of the pulse P2 is formed. When the voltage of the capacitor Cp reaches the peak potential Vp3, the switch SW45 of the clamp circuit 140 is turned on according to the control signal CSW45. Because of the diode D22, a current does not flow in a direction opposite to a direction of the supply current. Therefore, the switches SW22 and SW24 are turned off at an arbitrary timing until a turn-off timing of the switch SW45 after the voltage reaches the peak voltage. In the falling period PF2, electric charges q to Cr2VS/2, i.e., power are recovered from the capacitor Cp to the capacitor Cr2. In the clamp period PCL2, the potential GND of the clamp circuit 140 clamps the voltage of the capacitor Cp to the ground potential GND and maintains the display electrode capacitor Cp at the ground potential GND. Thereafter, the switch SW45 is turned off according to the control signal CSW45.
As described above, the driver control circuit 51 supplies data related to the display electrodes X and Y related to an off cell to the sustain circuits 63 and the sustain circuit 67. In the first falling period PF1 of first discharging of a sustain pulse, electric energy may be supplied to the capacitor Cp between the display electrodes X and Y related to the off cell and recovered. In this case, when the pulse power supply and recovery circuit 130 is arranged, the control signal generating circuit 604 supplies control signals to the switches SW31 to SW42 in a sustain period at a low load, i.e., to apply application voltages from the power recovery capacitor Cr3 to only cells in a row in which cells at a predetermined percentage of all the cells, for example, cells the number of which is ½ or more the total number do not emit light, i.e., do not perform address discharging. As a matter of course, regardless of a display load, electric energy may be supplied to and recovered from all the lines at once in the first discharge falling period PF1 of a sustain pulse. In this case, the pulse power supply and recovery circuit 130 is arranged to supply control signals to the switches SW31 to SW42 such that application voltages are applied from the capacitor Cr3 to all the display electrodes. It is assumed that electric charges of a voltage Vo/2 are accumulated in the power recovery capacitor Cr3.
In the first falling period PF1 to the potential Vs of the pulse P1, when the switches SW31 and SW33 are turned on according to the control signals Csw31 and CSw33, a current flows from the display electrode capacitor Cp to the capacitor Cr3 through the switch SW33, the diode D31, and the resonant inductor L3 which constitute a path 1, a voltage between both the terminals of the capacitor Cr3 slightly decreases, and a first falling edge of the pulse P1 is formed. When the voltage of the capacitor Cp reaches a peak potential Vp2, the switch SW42 of the clamp circuit 140 is turned on according to the control signal CSW42. Because of the diode D31, a current does not flow in a direction opposite to a direction of the supply current. Therefore, the switches SW31 and SW33 are turned off at an arbitrary timing until a turn-off timing of the switch SW42 after the voltage reaches the peak voltage. The peak voltage Vp2 is slightly higher than the potential Vs. In the falling period PF1, electric charges q to Cr3Vo/2, i.e., power are supplied from the capacitor Cr3 to the capacitor Cp. In the clamp period PCL2, the potential Vs of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential Vs and maintains the display electrode capacitor Cp at the potential Vs. Thereafter, the switch SW42 is turned off according to the control signal CSW42.
In the first falling period PF1 to the potential Vs of the pulse P2, when the switches SW32 and SW34 are turned on according to the control signals CSW32 and CSW34, a current flows from the display electrode capacitor Cp to the capacitor Cr3 through the switch SW32, the diode D32, and the resonant inductor L3 which constitute a path 2, a voltage between both the terminals of the capacitor Cr3 slightly increases, and a first falling edge of the pulse P2 is formed. When the voltage of the capacitor Cp reaches a peak potential Vp2, the switch SW42 of the clamp circuit 140 is turned on according to the control signal CSW42. Because of the diode D32, a current does not flow in a direction opposite to a direction of the supply current. Therefore, the switches SW32 and SW34 are turned off at an arbitrary timing until a turn-off timing of the switch SW42 after the voltage reaches the peak voltage. In the falling period PF1, since the capacitor Cp is not discharged, electric charges q to Cr3Vo/2, i.e., power are recovered from the capacitor Cp to the capacitor Cr3. In the clamp period PCL2, the potential Vs of the clamp circuit 140 clamps the voltage of the capacitor Cp to the potential Vs and maintains the display electrode capacitor Cp at the potential Vs. Thereafter, the switch SW42 is turned off according to the control signal CSW42.
In the pulse power supply and recovery circuit 110, the switch SW13 and the diode D11 may be realized by one transistor, and the switch SW14 and the diode D12 may be realized by one transistor. Similarly, in the pulse power supply and recovery circuit 120, the switch SW23 and the diode D21 may be realized by one transistor, and the switch SW24 and the diode D22 may be realized by one transistor. The same is applied to the pulse power supply and recovery circuit 130. The diodes D11, D12, D21, D22, D31, D32, and the like may not be provided. In such a case, the turn-off timings of the switches connected to the anodes of the respective diodes must be set to time of reaching peak voltages in the processes in the respective paths.
In place of the resonant inductor L1 arranged in the two paths 1 and 2 as a common element, resonant inductors may be independently arranged in the paths 1 and 2 in series with each other. In place of the resonant inductor L2 arranged in the two paths 1 and 2 as a common element, resonant inductors may be independently arranged in the paths 1 and 2 in series with each other. The same is applied to the pulse power supply and recovery circuit 130. As an alternative configuration, in the pulse power supply and recovery circuits 110, 120, and 130, some equal inductances of the inductances of the resonant inductors L1, L2, and L3 may be replaced with one common inductor. As an alternative configuration, in place of the resonant inductors L1, L2, and L3, one common inductor may be arranged.
In the pulse power supply and recovery circuit 110, in place of the switches SW13 and SW14, a changeover switch having one terminal connected to the capacitor Cp and the other terminal switched between the path 1 and the path 2 may be arranged. The same is also applied to the recovery circuits 120 and 130.
In this manner, according to the embodiment, in one pair of pulses, power is supplied from the capacitors Cr1 and Cr2 to the display electrode capacitor Cp, and most of power can be recovered from the capacitor Cp to the capacitors Cr1 and Cr2. Except for power consumed in sustain discharging, some degree of power supplied to the display electrodes X and Y can be recovered to the power recovery capacitor Cr3. In this manner, a power consumption of the display apparatus 10 can be suppressed to a low level.
According to another embodiment, only one or two of the pulse power supply and recovery circuits 110, 120, and 130 may be arranged in each of the sustain circuits 63 and 67.
It will be understood by an expert in this field that the present invention can be applied not only to one pair of pulses having asymmetrical waveforms but also to one pair of pulses having normal symmetrical waveforms.
The embodiments described above, a PDP is merely cited as a typical example. Combinations of the constituent elements of the embodiments, modifications of the embodiments, and variations of the embodiments are apparent to persons skilled in the art. It is apparent to the persons skilled in the art that the embodiments can be variously modified without departing from the principle of the present invention and the spirit and scope of the present invention described in the scope of the invention. For example, the present invention can be applied to an inorganic EL or electric paper which displays letters or the like by accumulating electric charges by applying a voltage thereto.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2005/001349 | 1/31/2005 | WO | 00 | 7/30/2007 |
