BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawings:
FIG. 1 is a sectional view showing a structure of an electric double layer capacitor according to a first embodiment of the present invention;
FIG. 2 is a longitudinal sectional view showing a state where the electric double layer capacitor according to the first embodiment of the present invention is received in an exterior case;
FIGS. 3A and 3B are graphs each showing charging and discharging characteristics of the electric double layer capacitor according to the first embodiment of the present invention;
FIGS. 4A to 4C are sectional views each showing a structure of an electric double layer capacitor according to a second embodiment of the present invention;
FIG. 5 is a graph showing dependency of a maximum current allowed to flow instantaneously into the electric double layer capacitor according to the second embodiment of the present invention on the number of small capacity single cells;
FIG. 6 is a sectional view showing a structure of an electric double layer capacitor according to a third embodiment of the present invention;
FIG. 7 is a schematic view showing a structure of electrodes of an electric double layer capacitor according to a fifth embodiment of the present invention;
FIG. 8 is a longitudinal sectional view showing a state where the electric double layer capacitor according to the fifth embodiment of the present invention is received in an exterior case;
FIG. 9 is a graph showing a dependency of an internal resistance on discharging time of the electric double layer capacitor according to the fifth embodiment and Comparative Examples 1 to 3 of the present invention;
FIG. 10 is a graph showing a charge and discharge efficiency depending on the discharging time of the electric double layer capacitor according to the fifth embodiment and Comparative Examples 1 to 3 of the present invention;
FIGS. 11A and 11B are schematic sectional views each showing a state of movement of electrons between a large capacity single cell and a small capacity single cell in the electric double layer capacitor according to the fifth embodiment of the present invention;
FIGS. 12A and 12B are schematic sectional views each showing a state of movement of electrons between a large capacity single cell and a small capacity single cell of parallel connecting capacitors of Comparative Example 3 of the present invention;
FIGS. 13A and 13B are equivalent circuit diagrams of the electric double layer capacitors according to Comparative Example 3 and the fifth embodiment of the present invention; and
FIG. 14 is a schematic view showing a structure of electrodes of an electric double layer capacitor according to a seventh embodiment of the present invention.