Claims
- 1. An electronic power supply system, comprising:
- an inverter coupled to and supplying power to a load;
- a first power source portion supplying power to said inverter;
- a second power source portion used in combination with said first power source portion for supplying the inverter with any deficiency of power supplied to the inverter from said first power source portion,
- said second power source portion including an alternating current power source and a voltage multiplying rectifier circuit, and
- wherein said first power source portion includes a solar power source, a system power control circuit connected to said solar power source, a voltage detector for detecting and generating a first signal VLD corresponding to the value of an input voltage to said inverter and an insolation sensor for detecting and generating a second signal Ee corresponding to the value of the output voltage of the solar power source,
- said system power control circuit further comprising, a switching element and controller circuit means including a signal processor responsive to said first and second signals for controlling the on/off duty cycle ratio D of said switching element, said switching element controlling the voltage amplitude of said first signal so as to set a predetermined maximum value Vset thereof, and wherein an initial value of said duty cycle ratio D is stored in a memory of said signal processor and is variable in increments of .DELTA.D, said increments further being initially set and stored in said memory, said signal processor duty cycle ratio D controlling the voltage amplitude of said first signal VLD such that VLD is decreased by said increments of .DELTA.D when Vset>VLD and increased when Vset<VLD, whereby the solar source operates at a maximum power point.
- 2. The electric power supply system according to claim 1 wherein said solar power source comprises a solar photovoltaic array.
- 3. The electronic power supply system according to claim 1 wherein said signal processor generates a digital output signal of said duty ratio D.
- 4. The electronic power supply system according to claim 3 and additionally including a digital to analog converter coupled to said digital output signal from said microcomputer for generating an analog output signal of said digital output signal of said duty ratio D, a first waveform generating circuit having a predetermined operation cycle and generating a ramp type waveform signal, a second waveform generating circuit having a predetermined fixed frequency and generating a clock type signal, a comparator circuit coupled to said analog output signal and said ramp type waveform signal and generating a comparison output signal therefrom, a flip-flop circuit coupled to said clock type signal and generating a rectangular type output signal, and a digital logic gate circuit coupled to said comparison output signal and said rectangular type output signal and generating a signal for controlling the switching operation of said switching element.
- 5. The electronic power supply system according to claim 4 wherein said ramp type waveform signal comprises a sawtooth signal.
- 6. The electronic power supply system according to claim 3 wherein said signal processor comprises a stored program microcomputer.
- 7. The electronic power supply system according to claim 4 wherein said digital logic gate circuit comprises an AND gate.
- 8. The electronic power supply system according to claim 4 wherein said switching element comprises a semiconductor switching element.
- 9. The electronic power supply system according to claim 4 wherein said switching element comprises a MOSFET type switching element.
- 10. The electronic power supply system according to claim 1 wherein said signal processor means control a start and a stop operation of said system power control circuit in response to a predetermined value of said second signal Ee.
- 11. The electronic power supply system according to claim 1 wherein said signal processor controls a start operation of said power control circuit in response to said second signal Ee and having a value Ee>Eo, where Eo comprises a value stored in said memory necessary for activation of said system power control circuit and where VLD>0 indicates that said load is operating.
Priority Claims (2)
Number |
Date |
Country |
Kind |
3-90572 |
Apr 1991 |
JPX |
|
4-90963 |
Apr 1992 |
JPX |
|
Parent Case Info
This application is a continuation, of application Ser. No. 07/870,891, filed on Apr. 20, 1992, now abandoned.
US Referenced Citations (5)
Number |
Name |
Date |
Kind |
4750099 |
Inoue et al. |
Jun 1988 |
|
4750102 |
Yamano et al. |
Jun 1988 |
|
4785226 |
Fujisawa et al. |
Nov 1988 |
|
4794272 |
Bavaro et al. |
Dec 1988 |
|
5034871 |
Okamoto et al. |
Jul 1991 |
|
Non-Patent Literature Citations (1)
Entry |
"Technical Digest of the International PVSEC-5" Kyoto, Japan 1990. |
Continuations (1)
|
Number |
Date |
Country |
Parent |
870891 |
Apr 1992 |
|