The present invention relates to an electrical circuit and in particular a combined amplifier and attenuation circuitry, especially for high frequency applications.
Amplifiers are well known and widely used in different applications with a need for amplifying signals.
In some applications, if there is a need for high and low gain modes, an amplifier 10 followed by a step attenuator 11 can be used, as illustrated in
The closest prior art disclose combinations of amplifiers and attenuators. For example: WO 96/31946, which relates to a non-linearity of a voltage-controlled non-linear amplifier/attenuator, is compensated by placing a non-linear circuit in the feedback path of an operation amplifier of a linearizer. The circuit includes one or more differential amplifiers connected in parallel. A pure attenuation mode circuit is not concerned.
According to GB 2 57 907, a high-frequency switching circuit is arranged comprising a high-frequency amplifying transistor for amplifying a high-frequency signal applied thereto, a switching diode connected between a power supply and a collector of the high-frequency amplifying transistor in the forward direction with respect to a current flowing into the collector through the diode, first means for deriving an output signal of the high-frequency switching circuit through the switching diode, and second means for causing the high-frequency amplifying transistor to stop its high-frequency amplifying operation to perform its attenuation operation. Thus, this invention relates to a switching arrangement with attenuation ability.
The main object of the present invention is to provide a novel circuit design, which eliminates the need for designing and implementing both an amplifier and an attenuator separately. The solution according to the preferred embodiments of the present invention allows minimal power consumption for the attenuator mode, which reduces heat in the circuit. Power and heat reductions are desired to be as low as possible. Additionally, the EMC-problem as mentioned earlier is solved, as the current path is controllable. Moreover, the solution according to the preferred embodiments saves space on integrated circuits.
The above problems are solved and advantages are achieved using a novel circuit design in which an amplifier circuit is provided with attenuator functionality and a control circuit.
Thus, in one preferred embodiment of the invention, the circuit comprises an amplifier having an input and an output, first switching arrangement and a second switching arrangement. The first switching arrangement is arranged between the input and ground and the second switching arrangement arranged between the output and ground. Means for controlling the first and second switching arrangements is arranged and connects the input and output to the ground so that the amplifier attenuates the signal. Most preferably, switching arrangements are transistors. The means for controlling the first and second switches is a control circuit. In on embodiment, the control circuit operates as a bias controller and sets suitable gate/base voltage for the transistors in both operation modes. In a preferred embodiment, the control circuit is designed as a level shifter.
The invention also relates to an integrated circuit comprising an aforementioned circuit.
The invention also relates to an electrical circuit comprising a transistor, resistors, first set of capacitors, and chocks. The transistor has: a first terminal being grounded, a second terminal connected to an input signal to be processed through chokes and a capacitance, a third terminal for an output signal through second set of capacitors, a circuit of a capacitor and resistor connected between terminals the transistor to provide a bias through the resistors. Switching means are connected to the first and second terminals. Means for controlling a bias of the first terminal for turning off the transistor are arranged.
According to one aspect, the invention relates to a method of processing a input signal into two states, a first state comprising amplification of the input signal and a second state comprising attenuation of the input signal. The method comprises controlling a first switching arrangement connected to an input of an amplifier and a second switching arrangement connected to an output of the amplifier such that the input and output are grounded.
In the following, the invention will be further described in a non-limiting way with reference to the accompanying drawings in which:
In the following, the invention is detailed with reference to schematically embodied circuits using FETs (Field Effect Transistors). However, the invention is not limited to FETs and can be realized using any type of transistors with respect to the desired applications. Thus, depending on the transistor type, it is appreciated by the skilled person that the type and value of the peripheral components may vary.
The amplifying transistor T1 is grounded through its source. The input signal to be amplified, SignalIN, is connected to the gate of the transistor T1 through chokes L4 and L2 and capacitance C5. The output signal (SignalOUT) is decoupled from the drain of the transistor T1 through capacitors C1 and C3. A circuit comprising a capacitor C4 and resistor R1 is connected in series between the gate and the drain of the transistor T1 so as to provide a bias through a series of resistors R1 and Rg. The drain of the transistor T1 is furthermore grounded through bypass capacitor C2 and inductance L1.
The equivalence circuit of
The additional circuitry, which allows the amplifier circuit to operate as an attenuator comprises transistors T2 and T3 and a controlling circuit 200, which controls the switching transistors, T2 and T3. By changing the voltage in the node V1 as well as controlling the gate bias of the RF-transistor T1, it is turned on or off.
The control circuit 200 is connected to the gates of the transistor T1-T3. The sources of the transistors T2 and T3 are grounded and their drains are connected to the gate and drain of the amplifying transistor, respectively. The control circuit may be arranged to receive a control signal 201. The control circuit may also be substituted with an external control signal.
In the amplifier mode, the two transistors T2 and T3 are switched off by means of the control circuit 200 and the amplifying transistor T1 operates normally and the circuit operates as an amplifier.
To operate as attenuator, the transistors T2 and T3 are in conducting state by means of the control circuit 200. When T2 and T3 conduct, SignalIN is connected to ground through resistors RP1, choke L3 and RP2 and the amplifying transistor T1 is turned off. Thus, the signal through the entire circuit is attenuated.
The equivalence circuit of
Normally, a transistor has very different return loss depending on the gate voltage. In the circuit according to the present invention, the gate voltage varies between two max values. Consequently, it is of most important to have a network, which always allows good return loss regardless of the gate voltage (Vgate) of the transistor. For this reason, the resistor RP1 can be chosen to have a suitable value, e.g. in this embodiment close to 50Ω, in order to provide a good return loss at the input terminal 21 when the entire circuit operates as attenuator. Analogous is applicable to RP2 at the output terminal 22.
The control circuit 200 operates as a bias controller and sets suitable gate/base voltage for the transistors in both operation modes. The control circuit may be designed as a level shifter in one embodiment.
Table 1 discloses examples of the control signal and the amplifier transistor signal values:
Accordingly, a good amplification and attenuation is achieved.
The parameters L1, L2, L4, C1, C2, C3, C4, R1 and Rg in
The invention is not limited to the shown embodiments but can be varied in a number of ways without departing from the scope of the appended claims and the arrangement and the method can be implemented in various ways depending on application, functional units, needs and requirements etc.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/SE05/00150 | 2/7/2005 | WO | 00 | 1/4/2008 |