BRIEF DESCRIPTION OF THE DRAWINGS
The objects, features, and advantages of the invention will be apparent from the following more detailed description of certain embodiments of the invention and as illustrated in the accompanying drawings in which:
FIG. 1 is a top plan view of an eFuse in accordance with a first embodiment of the invention;
FIG. 2A is a cross-sectional view of the eFuse of FIG. 1; FIG. 2B illustrates the dimensions of the second area of the resistor shown in FIG. 2A;
FIG. 3 is a top plan view of an eFuse in accordance with a second embodiment of the invention;
FIG. 4 is a cross-sectional view of the eFuse of FIG. 3;
FIG. 5 is a top plan view of an eFuse in accordance with a third embodiment of the invention;
FIG. 6 is a cross-sectional view of the eFuse of FIG. 5;
FIG. 7 is a top plan view of an eFuse in accordance with a fourth embodiment of the invention;
FIG. 8 is a cross-sectional view of the eFuse of FIG. 7;
FIG. 9 is a top plan view of an eFuse in accordance with a fifth embodiment of the invention;
FIG. 10 is a cross-sectional view of the eFuse of FIG. 9;
FIG. 11 is a top plan view of an eFuse in accordance with a sixth embodiment of the invention; and
FIG. 12 is a cross-sectional view of the eFuse of FIG. 11.
DETAILED DESCRIPTION OF THE INVENTION
It is noted that various connections are set forth between elements in the following description. It is noted that these connections in general and, unless specified otherwise, may be direct or indirect and that this specification is not intended to be limiting in this respect.
The eFuses of the present invention can be used in a variety of applications, non-limiting examples of which include silicon-on-insulator complementary metal oxide semiconductor large system integration (SOI CMOS LSI) devices, bulk CMOS LSI devices, programmable read-only memories (PROMs), field-programmable gate arrays (FPGAs), programmable array logic (PAL) devices, and very large system integration (VLSI) chips with SRAM and/or DRAM.
FIGS. 1 and 2A show top plan and cross-sectional views, respectively, of an eFuse according to a first embodiment of the invention. The eFuse has a resistor formed on a shallow trench isolation (STI) substrate 25. The resistor has an outer portion 10 formed of polysilicon and an inner portion 12 formed of polysilicon germanium (poly-Si(1-x)Gex). The resistor also includes a metal silicide layer 14 over the outer 10 and inner 12 portions, defining a first area of nickel silicide on polysilicon and a second area of nickel silicide germanium (NiSi(1-y)Gey) on polysilicon germanium, respectively.
As an alternative to nickel silicide (NiSix), the metal silicide layer 14 can be selected from a number of types of other metal silicides, non-limiting examples of which include cobalt silicide (CoSix), titanium silicide (TiSix), palladium silicide (PdSix), platinum silicide (PtSix), ytterbium silicide (YbSix), and erbium silicide (ErSix), where x is 0.3 to 2.
As the term is used herein, an area is considered to be “embedded” in another area when its surface area is wholly or partially contained within the other area. For example, in the embodiment shown in FIG. 2, the second area (defined by inner portion of polysilicon germanium 12 and overlying portion of metal silicide 14) has a rectangular cross-section of which three sides contact the first area (defined by polysilicon 10 and overlying portion of metal silicide 14). In the embodiment of FIG. 6, discussed more fully below, the second area (defined by inner portion 32) has a rectangular cross-section of which two sides contact the first area (defined by outer portion 24). Other variations can be made without departing from the spirit of scope of the invention. For example, the second area may have a non-rectangular cross section having one or more of its surfaces contained within the first area.
Because the material of the second area is less thermally stable than the material of the first area, the second area is more likely to rupture when a programming voltage is applied. In the metal silicide layer 14 of the embodiment shown in FIGS. 1-2, for example, nickel silicide germanium (NiSi(1-y)Gey) present in the inner portion is less thermally stable than nickel silicide present in the outer portions. The lower thermal stability of the nickel silicide germanium material also enables the eFuse to rupture at lower programming voltages. Effective programming voltages typically range from about 1.8 to 2.5 V, as compared to 3.3 V typical of conventional eFuses. Another benefit is that one can reliably predict the location at which the eFuse will rupture, namely in the second area due to its lower thermal stability.
With reference to FIG. 1, exemplary dimensions of the resistor include a total length h1 of 200 to 5000 nm. The fuse length h2 may be from 100 to 1500 nm and the fuse width 1 from 10 to 150 nm. With reference to FIG. 2A, the depth of the resistor d, may be from 30 to 200 nm. With reference to FIG. 2B, the embedded second area 12 may have a length w of about 20-200 nm and a depth d2 of about 10-100 nm. The width of the second area 12 can be the same as the fuse width 1. It should be recognized that these dimensions are exemplary and not limiting. The actual dimensions of the eFuse and/or its components may vary from the exemplary dimensions given.
FIGS. 3 and 4 illustrate an eFuse in accordance with a second embodiment of the invention utilizing a fully silicided (FUSI) gate. The eFuse has a resistor formed on an STI substrate 25. The resistor has an outer portion of metal silicide, such as nickel silicide 18 (NiSi), and an inner portion of polysilicon 22 formed on the substrate 25 and extending less than the full depth of the nickel silicide 18 layer. The first area is defined by the thicker portions of the nickel silicide 18, while the second area is defined by the thinner portion of the nickel silicide 18 overlying the polysilicon 22. The depth of the nickel silicide in the thin portion can range from about 10-100 nm, for example. This thin layer of NiSi is less thermally stable than the thicker NiSi portions in the adjacent areas because thin NiSi layers tend to agglomerate. Therefore, the second area is more likely to rupture than the first area upon application of a programming voltage.
The eFuse of the second embodiment can be manufactured using the following steps. After gate electrode patterning and source/drain formation using a conventional CMOS process, the gate polysilicon is fully silicided by sputtered excessive Ni metal. This structure is known as FUSI. During FUSI formation, if a thin silicon oxide layer is present on top of the poly gate, NiSi growth is inhibited. In this embodiment, the thin layer of NiSi is generated only on the portion with the thin silicon oxide layer.
FIGS. 5 and 6 illustrate an eFuse in accordance with a third embodiment of the invention. The eFuse has a two-metal resistor formed on an STI substrate 25. The resistor has an outer portion of a first metal, such as cobalt silicide 24 (CoSi2), and an inner portion of a second metal, such as nickel silicide 32. The first area is defined by the cobalt silicide 24, while the second area is defined by the nickel silicide 32. The thin nickel silicide 32 inner portion is less thermally stable than the thicker cobalt silicide 24 outer portion. Therefore, the nickel silicide 32 is more likely to rupture than the cobalt silicide 24 upon application of a programming voltage. Non-limiting examples of other combinations of first and second metals that can be used include NiSi2 and Ni3Si; W and NiSi; TiN and NiSi; and TaC and NiSi, respectively.
The eFuse of the third embodiment can be manufactured using a dual metal gate process with a replacement gate. This process is similar to FUSI except that this process uses two types of metal. One portion of a dummy poly gate is replaced with the first metal (e.g., area 24 in FIG. 6), while another portion of the dummy poly gate is protected from the replacement using a hard mask (e.g., area 32 in FIG. 6). After formation of the first metal 24, the remaining dummy poly gate is fully silicided to form the second metal 32.
FIGS. 7 and 8 show top plan and cross-sectional views, respectively, of an eFuse according to a fourth embodiment of the invention. The resistor is prepared on a silicon-on-insulator (SOI) substrate 35. The insulator can be, for example, silicon dioxide (SiO2). The resistor includes an outer portion 40 formed of silicon and an inner portion 42 formed of silicon germanium (Si(1-x)Gex). The inner portion may have a length of about 20-200 nm and a depth of about 10-100 nm, for example. A metal silicide layer 14 is provided over the outer 40 and inner 42 portions. When nickel silicide is used as the metal silicide, the first area includes nickel silicide on silicon and the second area includes nickel silicide germanium (NiSi(1-y)Gey) on silicon germanium. NiSi(1-y)Gey of the second area is less thermally stable than NiSi of the first area, and therefore is more likely to rupture upon application of a programming voltage.
The structure of the fourth embodiment can be manufactured by embedded SiGe source/drain, which is now commercially used in the advanced CMOS process. An SOI substrate can be etched away in portion 42, followed by selective epitaxial growth of silicon germanium. The portion 40 can be protected from this etching and selective SiGe growth using conventional techniques.
FIGS. 9 and 10 show top plan and cross-sectional views, respectively, of an eFuse according to a fifth embodiment of the invention. The resistor is formed on a silicon-on-insulator (SOI) substrate 35. The resistor includes an outer portion 40 formed of silicon and an inner portion 43 formed of silicon germanium (Si(1-x)Gex) that is entirely surrounded by the silicon portion 40. The inner portion 43 may have a length of about 20-200 nm and a depth of about 10-100 nm, for example. The thickness of the silicon in the area above the inner portion 43 can be from about 5 to about 30 nm. A layer 14 of metal silicide, such as nickel silicide, is provided over the silicon 40, defining a first area of nickel silicide on silicon and a second area of nickel silicide on silicon on silicon germanium (Si(1-x)Gex). NiSi of the second area, which has silicon germanium underneath, is less thermally stable than NiSi of the first area, and is more likely to rupture upon application of a programming voltage.
The eFuse of the embodiment shown in FIGS. 9 and 10 can be manufactured using commercially available substrates having five layers of silicon, oxide, silicon, silicon germanium, and single crystal silicon. The eFuse of this embodiment can be manufactured using steps similar to those described above for the fourth embodiment, with the difference being that selective SiGe epitaxial growth is followed by Si epitaxial growth.
FIGS. 11 and 12 show top plan and cross-sectional views, respectively, of an eFuse according to a sixth embodiment of the invention. The resistor is formed on an insulator substrate 35. A layer of silicon germanium 52 is provided on the substrate 35. An outer portion 50 is formed of silicon and an inner portion 55 is formed of nickel silicide germanium (NiSi(1-y)Gey). The inner portion can have a length of about 20-200 nm and a depth of about 10-100 nm. A metal silicide layer 14 is provided over the silicon areas 50, defining a first area of nickel silicide on silicon and a second area of nickel silicide germanium (NiSi(1-y)Gey) on silicon germanium. NiSi(1-y)Gey of the second area is less thermally stable than NiSi of the first area, and therefore is more likely to rupture upon application of a programming voltage.
The eFuse of the embodiment shown in FIGS. 11 and 12 can be manufactured using commercially available substrates, SGOI substrates, having five layers of silicon, silicon oxide, silicon, silicon germanium, and single crystal silicon on top. The eFuse of this embodiment can be manufactured by Si-etching portion 55, followed by a conventional CMOS process, which includes a Ni SALICIDE process. Following the salicidation process, NiSi(1-y)Gey can be generated over the SiGe layer, and NiSi can be generated over the Si layer.
While particular embodiments of the present invention have been described and illustrated, it should be understood that the invention is not limited thereto since modifications may be made by persons skilled in the art. The present application contemplates any and all modifications that fall within the spirit and scope of the underlying invention disclosed and claimed herein.
Patent Application
20080067629
