Patent Grant
6897528
This invention relates generally to a means of providing a high value floating resistor for integrated electrical circuits and a method of producing such a high value floating resistor. More particularly, the invention relates to a circuit arrangement that provides for coupling to a grounded resistance device such that the circuit arrangement presents a high value resistance between two floating, or non-grounded, nodes of the circuit arrangement.
The physical constraints of integrated circuits do not allow for the inclusion of standard fixed resistors as used in non-integrated electrical circuits. However, in various applications, the use of resistors, or resistance devices, in an integrated circuit is beneficial.
As a result, various techniques have been employed in order to provide an electrical resistance device in an integrated circuit that may be manufactured during the process of manufacturing the integrated circuit device.
Most commonly, poly silicon was used to provide an electrical resistance in integrated circuit arrangements. Whilst this technique is feasible, poly silicon is limited in the range of electrical resistance it can present to the order of 1 to 3 kΩ's whilst at the same time consuming a relatively large region of silicon associated with widespread end resistance value.
Alternatively, active devices such as MOSFET devices have been used in a particular arrangement such that they present an electrical resistance between two nodes. Use of these devices has enabled the provision of electrical resistances in the order of 500 to 600 kΩ's.
Whilst the use of MOSFET devices resulted in a significant improvement with respect to the range of electrical resistance that could be generated in an integrated circuit, the arrangement of these devices requires that one node of the resistance device be coupled to ground, or the circuit substrate.
In various applications, there is a requirement for circuits with large time constants. As the ability to provide capacitive devices in integrated circuits is limited, there is a requirement for larger values of electrical resistance to satisfy the time constant requirements. Additionally, there is also a need for a high value electrical resistance device that has floating terminals.
In one aspect, the present invention provides an arrangement of integrated circuit devices including two matched transistors each in a diode connected configuration operating in the saturation region, the arrangement providing for coupling the transistors to a free terminal of at least one grounded resistor such that the circuit arrangement presents an electrical resistance between two non-grounded nodes of the circuit arrangement.
The circuit arrangement thus effectively converts the at least one grounded resistor coupled to the transistors to a floating resistance device wherein both terminals of the resistance device are available for use in an integrated circuit.
The grounded resistor may be of any type including a passive resistor constructed from poly silicon. However, in a preferred embodiment, the grounded resistor is a transistor operating as an active resistance device.
The magnitude of the electrical resistance presented between the two non-grounded nodes of the circuit arrangement is dependent upon the magnitude of the grounded electrical resistance coupled to the transistors of the circuit arrangement. In one particular circuit arrangement, the electrical resistance presented between the two non-grounded nodes of the circuit arrangement is equivalent to approximately twice the grounded electrical resistance coupled to the transistors. There may be any number of grounded resistors coupled to the transistors in a cascade arrangement thus determining the magnitude of the electrical resistance presented between the two non-grounded nodes of the circuit arrangement.
In a particularly preferred embodiment, two grounded transistors operating as active electrical resistance devices are coupled respectively each of the matched transistors of the circuit arrangement. In this embodiment, the transistors are MOSFET devices with their gate terminals coupled together to form a current mirror arrangement.
In this preferred form, the magnitude of the electrical resistance presented between the two non-grounded nodes of the circuit arrangement may be in the Giga-ohm range.
At times, the properties between the floating terminals and ground may include parasitics.
As a result of the circuit arrangement including the two diode connected matched transistors, the electrical resistance presented between the two non-grounded nodes of the circuit arrangement will be dependent upon the channel length modulation parameter, λ. As the channel length modulation parameter is process dependent, the magnitude of the electrical resistance presented between the two non-grounded nodes of the circuit arrangement will also be process dependent.
The skilled person in the art will appreciate that the electrical resistance is dependent on the output conductance of the device and the use of λ is by way of a preferred arrangement only.
Reliance of the magnitude of the electrical resistance presented between the two non-grounded nodes of the circuit arrangement upon the process used to implement the integrated circuit is limiting. Accordingly, in a particularly preferred embodiment, the grounded resistors in the form of MOSFET devices with their gate terminals coupled together also have their gate terminals coupled to a third MOSFET device in a diode connected configuration to form a current mirror arrangement. The third MOSFET device is coupled to a current source and operable to supply an electrical current to the current mirror arrangement thus determining the magnitude of the electrical resistance presented by the grounded electrical resistance devices. As a result, in this particularly preferred embodiment, the magnitude of the electrical current supplied to the current mirror arrangement determines the magnitude of the electrical resistance presented between the two non grounded nodes of the circuit arrangement. Thus, it is possible to compensate or tune for the effects of the circuit arrangements dependence upon the channel length modulation for the particular process of manufacturing the integrated circuit by predetermining the electrical current supplied to the current mirror arrangement of the grounded active electrical resistance devices.
In another aspect, the present invention provides a method of determining the electrical resistance between two non-grounded nodes of an arrangement of integrated circuit devices including two matched transistors each in a diode connect configuration with each transistor coupled respectively to a grounded active resistance device, the active resistance devices forming a current mirror configuration with the gate terminal of each grounded active resistance device coupled to variable electrical current source, the method including the steps of:
Calculating the electrical current to be supplied to the coupled gate terminals of the active grounded resistance devices to produce a requisite conductance for each of the grounded active resistance devices according to the relationship:
gd=λId/(1+λVds)≈λId
where
The invention is now described by way of example with reference to the accompanying drawings in which:
The following detailed description of the invention refers to the accompanying drawings. Although the description includes exemplary embodiments, other embodiments are possible, and changes may be made to the embodiments described without departing from the spirit and scope of the invention.
It has been recognised that resistors and transconductors have an important role in a wide variety of applications such as signal processing and neural networks, which generally utilise analogue VLSI circuits.
In the following description it is assumed that the source and the back gate for the corresponding n and p type MOS transistor are connected together, unless it is specifically indicated otherwise.
The circuit arrangement of a preferred embodiment of the invention includes two diode connect matched transistors operating in the saturation region.
With reference to
Considering the currents I1 and I2, an expression for each of these currents may be written as:
I1=K/2(Vy−V2−VT)2 (1)
I2=K/2(Vx−V1−VT)2 (2)
where
K=μ0Cox(W/L), A/V2
μ0 is the carrier mobility, cm2/(VS);
Cox is the oxide capacitance per unit area, F/m2;
VT the MOS transistor threshold voltage, V;
The current passing through the circuit arrangement of
Iin=Iout=I2−I1 (3)
From equations (1), (2) and (3), Iout can be written as:
Iout=K/2[(Vx−Vy)−(V1−V2)][(Vx+Vy)−(V1+V2)]−2VT] (4)
The equivalent resistance, Reqv may be expressed as:
Reqv=(Vx−Vy)/Iin=(Vx−Vy)/Iout (5)
If we let
V1=Vx−VT+f(Vx) (6)
and
V2=Vy−VT+f(Vy) (7)
equation (4) can be written as:
Iout=K/2(f(Vx)2−f(Vy)2) (8)
This last equation (8) shows that the current passing through the circuit arrangement is independent of the MOS transistor threshold voltage and is a function of Vx and Vy and is proportional to K.
Circuit Arrangement Including Matched Transistors and Ideal Resistors
A complete circuit arrangement including two diode connected matched transistors operating in their saturation region is detailed in FIG. 2. The circuit arrangement of
In the instance of
The relationship between V2 and V1, while assuming an ideal resistor connected between V1 and ground, can be expressed as:
V1=R(2I2)=KR(Vx−V1−VT)2 (9)
Solving equation (9) for V1 provides two solutions, the feasible solution being:
V1=Vx−VT+[(1−(1+2KR(Vx−VT))1/2)/2KR] (10)
A similar expression for V2 can be expressed as:
V2=Vy−VT+[(1−(1+2KR(Vy−VT))1/2)/2KR] (11)
Comparing equations (10) and (11) with equations (6) and (7) respectively, f(Vx) and f(Vy) may be expressed as:
f(Vx)=(1−(X)1/2)/2KR (12)
f(Vy)=(1−(Y)1/2)/2KR (13)
where
X=1+2KR(Vx−VT)
Y=1+2KR(Vy−VT)
Substituting the values of f(Vx) and f(Vy) from equations (12) and (13) in equation (8), Iout may be written as:
Iout=(1/8KR2)[(1−(X)1/2)2−[(1−(Y)1/2)2] (14)
Assuming the square root of X>>1 and the square root of Y>>1, which is a valid assumption for large values of R, then equation (14) reduces to:
Iout=(1/8KR2)(X−Y) (15)
Substituting the values of X and Y in equation (15) with
Vx=VB+Vin/2; and
Vy=VB−Vin/2
equation (15) reduces to:
Iout=Vin/2R (16)
Equation (16) illustrates that the equivalent floating resistor value is independent of the process model parameters and is also independent of the MOS transistors threshold voltage. An expression for the equivalent resistance Reqv can be written by substituting equation (16) into equation (5), resulting in the expression:
Reqv=Vin/Iout=2R (17)
Equation 17 shows that the voltage-current relationship of the circuit arrangement of
With reference to
Circuit Arrangement Including Matched Transistors and Active Resistance Devices
The analysis presented above remains valid if the ideal resistors R are replaced by an active grounded resistor or conductance. The circuit arrangement can be used to convert a grounded active electrical resistance device to a floating resistance device by connecting two matched grounded resistors or conductances at V1 and V2. As the circuit arrangement of
A MOS transistor biased with relatively small current provides a very high value output conductance in the range of Giga-ohms (GΩ's). However, a MOS transistor output conductance is dependent on the channel length modulation parameter λ, which is generally defined as:
λ=(∈si/qNeffVds−VDsat)1/2/L (18)
Where
∈si is the dielectric constant of silicon;
Neff is the substrate doping density;
q is the electron charge;
Vds is the drain to source voltage;
VDsat is the drain saturation voltage;
L is the drain saturation voltage;
From equation (18), it can be recognised by those skilled in the art that λ is a process dependent parameter. Generally, it is not considered desirable to produce a circuit arrangement the operation of which relies upon a process dependent parameter. However, in the instance of the circuit arrangement of the preferred embodiment, the dependence on the process dependent parameter λ can be compensated by adjusting the value of the current supplied by transistor mnn to the transistors mn5 and mn6.
Using a simple transistor model which includes the channel length effect, the output conductance gd of mn5 or mn6 may be calculated at constant gate to source voltage as
gd=λId/(1+λVds)≈λId (19)
where Id is the drain current.
For an Id=1 μA and λ=1 mV−1 (extracted from level 13 model ammeters at 1 μA bias current), the equivalent floating resistor is 2 GΩ.
The circuit shown in
The circuit arrangement detailed in
As can be seen from
To demonstrate the use of the high value resistor in a practical design example, the circuit arrangement of the preferred embodiment was used in the design of an active low frequency, current controlled, band pass filter. This type of filter presents a major problem in motion detection and biomedical systems including pacemakers.
The band pass filter requirements selected were:
(i) 100 Hz bandwidth;
(ii) the first cut-off frequency at 1 to 10 Hz with the second at 100 Hz;
(iii) relatively high gain;
(iv) relatively small silicon area requirement with a capacitor of 1 pF; and
(v) moderate to low power consumption.
A band-pass filter with these requirements may be provided with the circuit arrangement detailed in
The transfer function of the circuit detailed in
H(s)=−A(s)(RCs)/(1+RCs) (20)
where A(s) is the Amplifier gain.
The simulation results for the circuit detailed in
The upper and lower cut-off frequencies for the ideal and floating resistor are slightly different due to the loading effect the floating resistor causes to the filter which is not included in the filter simulation with ideal resistors.
Conclusion
The present invention embodies many advantages including the provision of a circuit arrangement to convert fixed, or grounded resistors, to floating resistors. In particular, the circuit arrangement of the present invention provides for the coupling of active electrical resistance devices to provide a relatively high value electrical resistance between two non-grounded nodes of the circuit arrangement in the order of Giga-ohms.
A particularly preferred form of the invention provides for the magnitude of the floating electrical resistance to be determined by the magnitude of electrical current supply thus providing a means to select the magnitude of the floating electrical resistance by selecting the magnitude of electrical current supply.
The circuit arrangement requires relatively few active devices and consumes a relatively small amount of electrical power in operation.
The floating resistor of the present invention may be used in applications where a relatively high value resistor consuming a relatively small area of silicon, exhibiting relatively good linearity and wide dynamic range are required. Applications for such a device include neural networks, image processing and vision systems.
Further advantages and improvements may very well be made to the present invention without deviating from its scope. Although the invention has been shown and described in what is conceived to be the most practical and preferred embodiment, it is recognized that departures may be made therefrom within the scope and spirit of the invention, which is not to be limited to the details disclosed herein but is to be accorded the full scope of the claims so as to embrace any and all equivalent devices and apparatus.
In any claims that follow and in the summary of the invention, except where the context requires otherwise due to express language or necessary implication, the word “comprising” is used in the sense of “including”, i.e. the features specified may be associated with further features in various embodiments of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| PR7389 | Aug 2001 | AU | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCTAU02/01196 | 9/2/2002 | WO | 00 | 4/12/2004 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO0301977 | 3/6/2003 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6777752 | Osanai et al. | Aug 2004 | B2 |
| Number | Date | Country |
|---|---|---|
| 2 270 220 | Mar 1994 | GB |
| Number | Date | Country | |
|---|---|---|---|
| 20040256695 A1 | Dec 2004 | US |
