ELECTROCHEMICAL CELL BALANCING CIRCUITS AND METHODS

Abstract

A system for charging and/or discharging electrochemical cells of a pack that provides power to a load of an apparatus, such as a vehicle. The system can include a circuit coupled to an electrochemical cell of the pack and configured to charge and/or discharge the electrochemical cell at a plurality of times occurring throughout a period in which the apparatus is dormant. The system can have a lower power draw. The system can have automatic timeouts to stop charging and/or discharging the cells when an auxiliary battery is disconnected.

Description

TECHNICAL FIELD

Described herein are methods and systems for charging or discharging of electrochemical cells and, more specifically, to methods and systems for monitoring and managing the charging of electrochemical cells.

BACKGROUND

The need for monitoring and managing large arrangements of electrochemical energy storage cells for various applications is known, and systems for doing so typically include features such as voltage measurement, temperature measurement and battery cell balancing (e.g., equalization) either through selective cell dissipative discharging or charge redistribution.

Of particular interest are large-scale systems used for storing electrical energy for the propulsion of vehicles, such as electric or hybrid vehicles, as well as energy storage systems for electrical grid support and supplying power to remote locations. These systems are generally considered to have expectations of long service life and extremely low failure rates. For example, the proposed ISO 26262 standard and the ASIL standards for vehicles have very stringent requirements for safety and reliability, and in the future very stringent requirements be government-mandated.

Among other things, the system may need to take measurements of the cells, determine how to balance the cells, and compensate for different rates of self-discharge among the cells during the balancing operations. There are several existing methodologies to balance the cells. These include bleeding circuits to discharge some cells, individual charge circuits for each cell, switches to connect charge or discharge circuits to each cell, flying or switched capacitors that equalize the charge on different cells and other methods.

Conventional practices require a balancing circuit that is fast enough to be able to keep all of the cells balanced during the small fraction of the day when the vehicle is charging and/or being driven, and must be able to balance quickly enough to compensate for large periods of inactivity.

Periods of inactivity can be caused by an owner on vacation, an owner that drives multiple vehicles and therefore leaves one particular vehicle parked for extended periods of time, a vehicle in a dealer lot, a vehicle in a repair shop, or other reasons.

Having a larger, faster balancing circuit, however, creates some drawbacks for the measurement circuitry and decision-making process. The design must support higher currents which increase design costs and heat-dissipation requirements for the measuring and balancing units. Furthermore, as the balancing currents increase, so does the battery polarization voltage, and the voltage on the cells due to the internal resistance. Polarization voltage slowly decays after charging or discharging, and a true open circuit voltage may accordingly only be available for sensing several hours after charging or discharging the cells; thus, even if the balancing current is turned off temporarily when taking measurements, the polarization voltage can make comparisons between balancing and non-balancing cells even more difficult. In order to compensate for the polarization, either the system software must be even more complicated with accurate models for the cells, or balancing must be turned off sufficiently in advance of taking the measurements (thereby reducing the opportunities to make balancing decisions and or reducing the time during which balancing can occur).

SUMMARY

Some embodiments relate to a system for charging and/or discharging electrochemical cells of a pack that provides power to a load of an apparatus. The system includes a circuit coupled to an electrochemical cell of the pack and configured to charge and/or discharge the electrochemical cell at a plurality of times occurring throughout a period in which the apparatus is dormant.

Some embodiments relate to system for charging and/or discharging electrochemical cells of a pack. The system includes a controller configured to generate a control signal. The system also includes a circuit coupled to an electrochemical cell of the pack. The circuit is configured to charge and/or discharge the electrochemical cell in response to the control signal and to automatically stop charging and/or discharging the electrochemical cell after a predetermined time period.

Some embodiments relate to a system for charging and/or discharging electrochemical cells of a pack. The system includes a controller configured to generate at least one control signal and a plurality of circuits individually coupled to respective electrochemical cells of the pack to charge and/or discharge the electrochemical cells in response to the at least one control signal. The system is configured to draw no more than 100 mA on average from an auxiliary battery when in operation.

The foregoing summary is provided by way of illustration is not intended to be limiting.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a circuit for discharging an electrochemical cell, in which the circuit has an automatic timeout and an inputs for starting and stopping discharge, according to some embodiments.

FIG. 2 shows a circuit for discharging an electrochemical cell, in which the circuit has an automatic timeout and a single input for starting discharge, according to another embodiment.

FIG. 3 shows one implementation for implementing the circuit of FIG. 1 using a capacitor and a resistor to provide an automatic timeout.

FIG. 4 shows an implementation of the circuit of FIG. 2 having a capacitor and resistor to provide an automatic timeout and an amplifier for driving a transistor to discharge the cell.

FIG. 5 shows another implementation of the circuit of FIG. 1 using a capacitor and resistors to provide a timeout and an amplifier for driving a transistor to discharge the cell.

FIG. 6 shows another implementation of the circuit of FIG. 1 in which an op-amp integrator is used to produce an automatic timeout.

FIG. 7 illustrates a method and circuit for chaining together signals so that a refresh signal originating at a first cell can travel through all of the balancing circuits to every cell.

FIG. 8 shows an implementation that combines the features illustrated in FIG. 5 and FIG. 7.

FIG. 9 shows an implementation with an optocoupler for transmitting the signal from a chassis referenced potential to the bottom of the cell referenced signal chain.

FIG. 10 shows an implementation in which the optocoupler is powered using the supply available on the chassis of a vehicle.

FIG. 11 shows an implementation in which the optocoupler is powered directly using the supply for the slave devices.

FIG. 12 shows an implementation in which a separate pin is provided on the slave circuits so that the master can simply pulse voltage on a separate bus wire to keep the devices awake.

FIG. 13 shows an implementation with separate pins for pulse in and pulse out.

FIG. 14 shows an embodiment that uses an LTC6802 chip.

FIG. 15 shows a latching circuit setup so that if the chain turns off, the power is removed from the latching circuits and they turn off.

FIG. 16 shows a circuit and method of ensuring the chain can stay on with only periodic refreshes.

DETAILED DESCRIPTION

In view of the above, it is accordingly highly desirable to have a method and a system that balances the charge of the electrochemical cells of a vehicle, even when the vehicle is dormant, thereby allowing smaller balancing circuits, less heat dissipation, and simplifying any software needed to balance the cells. As used herein, the overall concept of balancing the cells while the vehicle is dormant will be referred to as “sleep balancing.”

The systems, circuits and methods described herein are capable of implementing balancing of electrochemical cells through charging or discharging of the electrochemical cells repeatedly even when a vehicle (or other apparatus) is dormant. A dormant state for a vehicle can refer to a state in which the vehicle is not being driven (e.g., no power is provided from the battery pack to the motor to drive the vehicle), the vehicle is not turned on, and the battery pack is not being charged (e.g., no power is flowing into or out of the battery pack). The system may balance continually while a vehicle is dormant, and charging and/or discharging of cells may be enabled at a plurality of times throughout a period in which the apparatus is dormant. A controller implementing a balancing algorithm may control circuits to charge and/or discharge individual cells for a relatively short, pre-determined amount of time. This operation may be repeated at various intervals to maintain the cells of the battery in a desired state of charge without drawing a high amount of current. The system may have the ability to quickly turn balancing “on” and “off” while the vehicle is on in order to make cell measurements with and without balancing “on.” These systems, circuits and methods can ensure that if the starter battery is disconnected for service, the balancing system is disabled within a reasonable amount of time. The system may have a very low average power draw, enabling an auxiliary battery such as the 12V starter battery to provide power for sleep balancing even if a vehicle remains dormant for long periods (e.g., days, months or more).

There are several implementations and combinations thereof that can be used to achieve one or more of these features.

Method 1:

A battery pack may have multiple electrochemical cells in series. A representative cell is illustrated in FIG. 1 as Cell1, and has an associated discharge resistor R1 and discharge switch Q1. The discharge switch Q1 (represented by a MOSFET, but any controllable switching device may be used), is controlled by a control circuit 2 that can be turned on, or turned off. When circuit 2 is commanded “on”, (by closing S1), Q1 is turned on by the CTRL signal. If S1 is open and S2 is closed, the CTRL signal will turn off Q1. If Q1 is turned on by closing S1, and then both S1 and S2 are opened, the CTRL signal will turn itself off after a predetermined time period, opening Q1. When Q1 is on, Cell1 is discharged through R1, balancing Cell1 by bringing it to a lower charge level to balance the pack. Similar control circuits 2, discharge resistors and discharge switches may be provided for each of the cells of the battery.

Methods for selecting which cells to discharge are known to those of ordinary skill in the art, and are therefore not described herein. A controller 4 may implement any suitable technique for balancing cells, and may provide control signals to terminals ON and OFF of control circuit 2 (e.g., by controlling switches S1 and S2).

The circuit shown in FIG. 1 has a way to be turned on through switch S1. Having a quick way to turn the circuit off (e.g., using S2) is optional. The MOSFET shown as being used for switch Q1 could be replaced with other switching devices including, but not limited to, N or P channel FETs, NPN or PNP transistors, etc. Switches S1 and S2 can be any type of switching devices including, but not limited to: optocouplers, multiplexer inputs or outputs, opto-isolated relays, transistors, FETs, etc.

The control circuit 2 of FIG. 1 has the following capabilities: the ability to turn on the balancing, very low current draw when the balancing is off, the ability to turn off balancing after a predetermined timeout, if left on, and the ability to turn off balancing quickly enough to make measurements.

FIG. 2 shows an implementation with only the ability to turn the control circuit on through S1, and no ability to quickly turn it off.

The predetermined period for the control circuit 2 to turn itself off should be a long enough period to allow for low current draw off of the 12V battery. If the period is short, any circuitry involved in refreshing the balancing command and turning on all S1 switches would need to be turned on more frequently, and the average 12V current draw from the starter battery would increase.

If the refresh period is slow, and there is no switch such as S2 to quickly turn the system off to make measurements, current may be flowing through the cell when a measurement is taken. Accordingly, measurements may need to be sufficiently accurate when the battery is balancing to be used for all functions for which the measurements are used. Alternately, when the vehicle is turned on, balancing could be permanently disabled, but this would decrease the amount of time when balancing could be enabled.

FIG. 3 shows an implementation of the control circuit 2 of FIG. 1 with an automatic timeout. When S1 is closed, the capacitor C1 charges up to the Cell1 battery voltage and turns Q1 on very quickly. When S2 is closed, C1 discharges quickly, turning off Q1 and stopping the discharge of Cell1. If S1 is closed and then opened, C1 is charged up and Q1 turns on. With S1 open C1 slowly discharges through R2, and after a long enough period, C1 will discharge sufficiently so that Q1 turns off and balancing ceases.

FIG. 4 shows the addition of a comparator/amplifier after the resistor/capacitor timing circuit. This allows Q1 to be replaced with a part that requires a lower turn-on voltage, or more current, such as a NPN transistor. It also helps ensure that whatever component is chosen for Q1 does not slowly go from saturation to active mode to “off,” but instead turns off quickly when the voltage across C1 hits a specific threshold. The circuit to operate as a comparator or amplifier can be a comparator, an operational amplifier in a Schmidt trigger configuration, a few discrete FETs or transistors, or any other circuit or component that amplifies the current and/or ensures that the circuit turns on and/or off at specific thresholds. As used herein, the term “amplifier” will be used to encompass both amplifiers and comparators, as a comparator can be considered to be an amplifier that produces saturated output signals.

FIG. 5 shows another implementation of the circuit of FIG. 1 using a capacitor and resistors to provide a timeout and amplifier circuitry including transistors Q3 and Q2 for driving a transistor Q1 to discharge the cell. Switches S1 and S2 can charge or discharge capacitor C1, respectively. When capacitor C1 is charged, it will turn on Q3 with very low base current. This will turn on Q2 which will then turn on Q1. Due to the very high resistance of R2 and R3, C1 will remain on for a considerable amount of time after it is left on by closing and then opening S1.

There are other examples of circuits with automatic timeouts that could be used. For example, an op-amp integrator circuit with an output buffer can be used to obtain more specific timing than that provided by the capacitor and resistor combination illustrated above, as well as higher output current drive.

FIG. 6 shows an op-amp integrator with transistors Q2, Q3 that convert the output of the op-amp to a discrete on/off signal. Resistors R3 and R4 form a bias network so the circuit is integrating the input voltage relative to the bias voltage (not the input voltage relative to 0V). The input voltage can be quickly changed by closing S1 or S2, or slowly changed by pulling up the input through R2. When S2 is closed, the output of the op-amp (e.g., U1A) will very quickly discharge to 0V, turning off Q2, which in turn turns off Q3 and then Q1, disabling balancing. When S2 is open and S1 is closed, the output of the op-amp quickly charges to the battery voltage, enabling Q2, which then enables Q3 and Q1, turning on balancing. When neither S1 nor S2 are closed, the output of the op-amp very slowly discharges towards 0V by virtue of the combination of C1 and R2, turning off Q2 then Q3 and Q1 after a set amount of time. Whenever Q1 is on, the cell is being balanced through R1, and whenever Q1 is off, balancing is off.

Current mirrors with buffers can be used for constant rates of charge or discharge for the capacitor. Latching circuits can be used with timing chips, and there are several circuits which can be used with this methodology.

In order to use this method for sleep balancing, the controller 4 may periodically “wake up” and refresh the balancing commands. The average current draw from the 12V battery will be based on how frequently the system refreshes the balancing command, the duration that the system is turned on to refresh the balancing command, and the current drawn while refreshing the command. That is:

I_avg=I_on*T_on/Period.

There are several strategies to minimize T_on. In a master/slave system it is possible to have the control circuit at each cell store the balancing command. With this technique no time is needed for the master unit to communicate with the slave units unless the overall balancing command is changing. If the slave units go through a minimal startup routine and then refresh the balancing command as quickly as possible, they can be turned back off in a very short amount of time. If the master must communicate the balancing command to the slave units, care can be taken in minimizing the amount of bus traffic necessary to convey this command.

The period can be increased by increasing the amount of time it takes for the circuits to shut themselves off which allows for less frequent refresh cycles, resulting in lower average current. By using Darlington transistors, or FETs optimized for low currents, and/or larger resistors discharging the capacitors, the capacitors will discharge more slowly resulting in longer timeout periods. Ultra low current op-amps or other devices can also be used to ensure a very slow capacitor discharge rate. Larger capacitors will hold more charge and will also allow the circuit to be refreshed less frequently.

The average current can be minimized in several ways. For example, any circuitry that is not required to be on can remain off until after the balancing has been refreshed.

In the case of a master/slave system, the master can be split into two sections. One section is always “on”, and contains a timer used only to pulse the slaves to continue the balancing command. The second section of the master is kept “off” during most or all of the pulses, and is “on” when required by the vehicle, or based on a second period to take more measurements and correct any balancing commands. The full master system would have the ability to command the pulses on or off before shutting down the portion of the circuitry that may be turned off depending on whether or not any balancing is required, and on the state of the starter battery. (It is also possible to have the entire master unit be enabled, but this increases the current required to refresh the balancing.)

During the refresh pulses, a system with digital logic and non-volatile memory may be used to refresh all of the balancing signals. This is performed because some cells which are balancing need to have the S1 lines pulsed to keep the balancing on for the cells which must be balanced. For cells that are not to be balanced, the S1 lines should not be pulsed. The portions of the circuit that are pulsed on may need to remember which S1 lines to refresh and which lines to keep off; hence the use of non-volatile memory.

In a master/slave system, the entire slave may be turned on, and a slave microcontroller could serve as the memory and logic portions. Secondary controllers, low power memory devices that always remain on, or other methods may be used to memorize and pulse the correct S1 lines. It is also possible to turn on the entire system, but higher current would be used.

Similar methods can be used in non-distributed systems where only a portion of the single battery management controller is awakened to refresh the balancing circuits.

As a summary of the above described implementation of method 1: Each cell has a balancing circuit. The circuit can be turned on, or off, but if left on it will eventually turn itself off. When sleep balancing, the system periodically wakes up all circuits involved with balancing and refreshes the balancing commands so that the balancing stays on for the desired cells. The full system periodically wakes up at a slower rate to be able to monitor and adjust the balancing process. Finally, if the 12V power to the system is removed, the system would not periodically refresh, and the balancing commands will stop in a reasonable amount of time (however long it takes for the balancing circuits to timeout), protecting the batteries from over-discharge.

Method 2:

In method 2, instead of needing to turn on a processor or logic device of controller 4 for the balancing circuits to refresh themselves, hardware may be set up to automatically refresh all of the cells that are currently balancing without needing the processor to actively refresh them.

FIG. 7 illustrates a method and circuit for chaining together signals so that a refresh signal originating at cell 1 can travel through all of the balancing circuits for every cell on a balancing device regardless of whether or not they are balancing. Note, the actual balancing circuitry is not shown. If R10A is pulled low relative to Cell1, Q4A turns on which in turn turns on Q5A. This pulls R10B low which turns on Q4B which turns on Q5B. This signal will travel up so that every circuit has a signal that can be used to refresh cells that are on. Note that the transistors in question can be replaced with FETs or other switching devices. Furthermore, other means of providing voltage translation can be used to transmit this signal up the cell stack.

FIG. 8 shows a combination of the balancing circuit of FIG. 5 and the signal chaining technique shown in FIG. 7. S1, S2, C1, Q3, Q2 and Q1 function as described above, allowing the circuit to be turned on, off, and to automatically timeout when left on. Q4 and Q5 can be used to transmit a signal from cell to cell up the entire battery stack. When the signal is sent, if Q1 is on, the base of Q6 is pulled low and Q6 will turn on. Q4 will be on because its base is pulled low through the refresh signal from the cell below. This pulls up the collector of Q6 which recharges C1 just as if s1 was closed. When the refresh signal is not being sent, Q4 will be off, and Q6 will be unable to recharge C1. If Q1 is off, Q6 will not be on, and C1 will not be recharged. With this circuit, the only action needed to refresh the balancing circuit is a very short duration pulse turning on Q4A for the bottom cell.

FIG. 9 shows an optocoupler U1 that may be used transmitting the signal from a chassis-referenced potential to the bottom of the cell-referenced signal chain.

FIG. 10 shows the optocoupler U1 being powered using the supply available on the chassis section. The chassis section is fully powered up to activate the chain. In this circuit, VR1 is a voltage regulator that not only supplies power to U1, but also supplies power to monitoring circuitry. While it is desired to turn U1 on during the pulse, it may not be desired to turn on all of the other circuitry which is not needed to refresh the balancing pulse, as doing so would draw unnecessary current. A master controller can send a pulse to all of the slave devices. The pulse is long enough to power up VR1 and then turn on U1. The power goes to U1, and to all devices on the regulated VR1 output. There is an optional pin labeled Disable Logic which could ensure that U1 can be disabled when the slave is fully on; this ensures that the refresh signal does not interfere with the ability to turn off the balancing using the S2 switch in FIG. 8. If, however, the transistor is sized appropriately in FIG. 8 such that a signal from S2 would override the refresh signal through Q6, the disable logic would not be needed.

FIG. 11 shows the optocoupler U1 being powered directly off of the supply for the slave devices. This allows a master controller to send a pulse to the power pins of all of the slaves. The pulse no longer needs to be long enough in duration to power up VR1, only long enough to power up U1. Furthermore, if R1A is sized properly, U1 can be powered up over a wide range of input voltages. Some of these input voltages could be low enough so that VR1 is not powered up at all. This allows a pulse to be sent on the power pin that only powers U1. By powering less circuitry, and by powering the circuitry for a shorter duration, less current is consumed off of the 12V system.

A variation of this idea would be to give U1 its own lower voltage regulator so that a lower voltage pulse could power up U1 without powering up the rest of the board.

FIG. 12 shows the same circuit, but a separate pin is provided on the slave circuits so that the master can simply pulse voltage on a separate bus wire to keep the devices awake.

FIG. 13 shows separate pins for pulse in and pulse out. This allows the pulse in and pulse out pins to be in series for different slaves. This means that with multiple slave devices, the current will flow into one U1, and then into the next U1 in series so the current does not add up. The current required for multiple slaves is the same current that would be required for a single slave. The multiple R1As on each slave can then be sized based on the system voltage and number of slaves in the system.

For Method 2, as with method 1, the average current can be calculated:

I_avg=I_on*T_On/Period.

For Method 2, T_on is greatly reduced because a short pulse can refresh all of the capacitors without waking up and initializing the memory and logic devices required in Method 1 which must individually refresh each cell. In Method 2, a short duration pulse can refresh all of the cells.

For Method 2, I_on can also be decreased substantially. FIGS. 11 through 13 show methods of decreasing the current required to refresh the system so that most of the slave devices can remain powered off while a pulse is sent only to the required circuitry.

The controller 4 may be configured to operate in a high power mode and a low power mode at different points in time. When in the high power mode, the controller 4 may generate a control signal to turn on switches S1 or S2 (FIG. 8). To reduce the amount of power used, the controller 4 may enter a low power mode for a period of time. In the low power mode, controller 4 need not generate the control signals to turn on the switch S1 to enable charging and/or discharging of the cell. Rather, as discussed above, the system can be configured to provide the refresh signal to the circuit to keep the cell balancing when the controller 4 is in the low power mode. The refresh signal may be generated by any suitable circuit, such as a timer circuit or other circuitry. Comparing Method 2 to Method 1, Method 2 has a much lower average power draw for the same period.

There is a trade off with period and circuit complexity or cost. In order to have a longer period in FIGS. 5 and 6, larger capacitors may be needed. It may be possible to achieve low power consumption using method 2 even with a shorter period. A shorter period would allow smaller capacitors or less expensive timeout solutions to be used.

Method 3:

Method 3 is a variation on Method 2 using Linear Technologies LTC6802 ICs or any similar battery management IC that contains a watchdog timeout to automatically disable balancing. The LTC6802 ICs are designed to be stackable, and they have voltage shifting topologies that allow the ICs to be placed in series. Communication takes place with the first LTC6802 IC, and then it transfers the levels to connect to the 2^nd LTC6802 which in turn can connect to another LTC6802 etc. The LTC6802 contains a watchdog timer so that if no communication takes place with the IC for 2.5 seconds, it will disable all balancing. Alternately, it can be placed into a low power non-monitoring mode while it continues to balance the cells as long as the watchdog does not expire. The LTC6802 uses 4 lines for communication following a Serial Peripheral Interface (SPI) communication scheme. Included is a chip select, a clock, a data line for transmission from masters to slaves: master out slave in (MOSI) and a data line for transmission from slaves to masters: master in slave out (MISO). In order to refresh a balancing command, the clock line may be toggled once every 2.5 seconds. There are several diagrams showing how to connect the LTC6802 to monitor multiple batteries in the datasheet, however all of the systems previously described are set up to be completely on, or completely off. No system has been disclosed previously to keep refreshing the watchdog timer while keeping most of the system off.

The board could be awakened once every 2.5 seconds to communicate with the LTC6802. However, similar methods to those used in method 2 may be used to only power up a small subset of the board.

The LTC6802 IC requires that all 4 SPI lines be left high when not in use to allow the unit to remain in the lowest possible power mode.

FIG. 14 demonstrates method to connect a LTC6802 to chassis-based communications as per the LTC6802 datasheet with the additional ability to perform sleep balancing. It has the ability to refresh the balancing signal while retaining the ability of the LTC6802 to have fast communication while on, and while meeting the balancing requirements of having very low average off current. The communication lines to the LTC6802 are labeled MOSI, MISO, CLK and CS and are shown on the right hand portion of the page. The LTC6802 is not shown. Signals on the left hand portion of the page would be chassis referenced signals that would to a microprocessor to facilitate communication with the LTC6802. U26 is a digital isolation circuit and U1 through U3 are optocouplers.

When the device is off, U1, U2 and U3 are off. U2 being off disconnects the GND from U26 so all pins of U26 are off and are at the LTC6802 VCC which ensures that U26 is drawing no power and the LTC6802 is in low power mode.

Under normal operation, U2 is turned on to turn on U26, U3 acts as the chip select which can be a slower than the clock and data lines, and U26 is used for communication with the LTC6802 for the faster clock and data lines. U1 is disabled so that it does not interfere with the clock signal for the LTC6802. Because the chip select line changes state less frequently than the other lines, it is acceptable to have a slower chip select line than the other lines.

When sending a pulse in sleep mode, U2 is off so the U26 GND pin is disconnected from LTC_GND. U3 is also off so all lines are at VCC. Pulsing U1 will bring the clock line low which resets the watchdog timer. Resistor R2 limits current that could backfeed U26 while the clock is being pulled low. A CMOS protection diode (not shown) from the U26 GND pin (anode) to the clock pin (cathode) on U26 could be used to further protect U26 ensuring that the U26 CLK line would not be pulled excessively below the U26 GND pin. As with Method 2, U1 can be fed from the power circuit before or after any regulators, or by itself through separate wires either in parallel or series with other slave devices. If the power pins are used, a transistor, FET or switch can turn off U1 to communicate by pulling pin 1 of U1 down to the chassis ground level.

Note, it is possible to use this method a digital isolator for all 4 lines instead of having U3 for the chip select line. It is also possible to use optocouplers for all communication lines instead of using the digital isolator. While U26 is shown drawing power from the LTC6802, it is also possible to power up U26 through a DC-DC converter as long as U26 pulls all the pins to the LTC VCC when off instead of to GND. Further variations on this method are possible.

The addition of U1 allows the LTC6802 to be refreshed without powering up the entire device. The addition of U2 ensures that U26 does not draw power off of the cells when the device is asleep.

Method 4:

Method 4 is similar to method 2 in the use of a signal chain and level shifting among the cells. It differs from method 2 in that the signal chain always needs to be active for the cells to be able to balance. In this method, latching circuits are used that stay on once turned on, and stay off when turned off. The signal chain is used to force the latching circuits off either by interrupting their power, or by sending the off signal if the chain is turned off. A circuit will automatically turn off the signal chain if not refreshed.

FIG. 15 shows a latching circuit setup so that if the chain turns off, the power is removed from the latching circuits and they turn off. R10, Q4, R11 and Q5 make up the chain going from one cell to the next. Flip flops, latches, or simple transistor combinations. among other designs, can make up the latching circuit shown in the block diagram, for storing the balancing command. VCC for the latching circuit is powered from the emitter of Q4 which is normally slightly lower in potential than the positive of Cell1. When the chain is turned off Q4A will no longer provide current and the latching circuit will be disabled.

FIG. 16 shows a technique for ensuring the chain can stay on with only periodic refreshes. U1 is periodically turned on. This charges up C1 which keeps R12 and Q6 turned on even after U1 is turned off Q6 in turn pulls down R10A which turns on Q4A and activates the chain. If U1 is not refreshed, C1 will discharge which will disable Q6 which then disables Q4 and the entire chain is turned off, disabling the sleep balancing.

In summary, sleep balancing can work in master slave systems or systems with an entire battery management system on a single board. It can operate by either waking up all of the circuitry on one a board to refresh a balancing command, or a very small portion of the circuitry. In a master slave system, the entire master can wake up, or a small portion can remain operating to send periodic pulses. Likewise the entire slave or a tiny portion may need to be activated to refresh the balancing signal. The refresh can either involve the processor turning on all of the signals to keep them on (Method 1), sending a signal up a chain to refresh all of the balancing signals (Method 2) or to keep the chain on to keep balancing enabled (Method 4), or sending a pulse to an integrated circuit to keep a watchdog timer from expiring (Method 3). In all cases the balancing circuitry can draw very low power from the 12V battery and allows it to operate in sleep mode for significant periods of time without discharging the 12V battery. For example, the system may draw no more than 100 mA on average when in operation. In some cases, the system may draw significantly less current, such as no more than 50 mA or no more than 2 mA on average. It allows all of the cells to remain balanced even if the car is primarily dormant. Finally if the 12V battery is removed, the balancing will stop within a reasonable amount of time to ensure that the cells are not over-discharged.

Additional Aspects

While various inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

For example, embodiments of controllers, such as controller 4, may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on any suitable hardware processor or collection of hardware processors, whether provided in a single computer or distributed among multiple computers. It should be appreciated that any component or collection of components that perform the functions described above can be generically considered as one or more controllers that control the above-discussed functions. The one or more controllers can be implemented in numerous ways, such as with dedicated hardware, or with general purpose hardware (e.g., one or more processors) that is programmed to perform the functions recited above.

Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.

Such computers may be interconnected by one or more networks in any suitable form, including a local area network or a wide area network, such as an enterprise network, and intelligent network (IN) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.

The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and/or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine.

In this respect, various inventive concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory, one or more floppy discs, compact discs, optical discs, magnetic tapes, flash memories, circuit configurations in Field Programmable Gate Arrays or other semiconductor devices, or other non-transitory medium or tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement the various embodiments of the invention discussed above. The computer readable medium or media can be transportable, such to that the program or programs stored thereon can be loaded onto one or more different computers or other processors to implement various aspects of the present invention as discussed above.

The terms “program” or “software” are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above. Additionally, it should be appreciated that according to one aspect, one or more computer programs that when executed perform methods of the present invention need not reside on a single computer or processor, but may be distributed in a modular fashion amongst a number of different computers or processors to implement various aspects of the present invention.

Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically the functionality of the program modules may be combined or distributed as desired in various embodiments.

Also, data structures may be stored in computer-readable media in any suitable form. For simplicity of illustration, data structures may be shown to have fields that are related through location in the data structure. Such relationships may likewise be achieved by assigning storage for the fields with locations in a computer-readable medium that convey relationship between the fields. However, any suitable mechanism may be used to establish a relationship between information in fields of a data structure, including through the use of pointers, tags or other mechanisms that establish relationship between data elements.

Note that the actual embodiment may be realized using discrete electronics, integrated circuits or the construction of the most or all of the entire system on a single application-specific integrated circuit (ASIC) specifically for this application.

Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and/or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and/or” as defined above. For example, when separating items in a list, “or” or “and/or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.

As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of and “consisting essentially of shall be closed or semi-closed transitional phrases, respectively.

Claims

1. A system for charging and/or discharging electrochemical cells of a pack that provides power to a load of an apparatus, the system comprising: a circuit coupled to an electrochemical cell of the pack and configured to charge and/or discharge the electrochemical cell at a plurality of times occurring throughout a period in which the apparatus is dormant.

2. The system of claim 1, wherein no power is drawn by the load from the pack when the apparatus is dormant.

3. The system of claim 2, wherein no current is flowing into or out of the pack when the apparatus is dormant.

4. The system of claim 1, wherein the apparatus is a vehicle and the load comprises a motor of the vehicle.

5. The system of claim 4, wherein the vehicle is dormant when the vehicle is turned off and the pack is not charging.

6. The system of claim 4, wherein the vehicle is dormant when the vehicle is turned off and no current is flowing into or out of the pack.

7. The system of claim 1, further comprising: a controller configured to generate a control signal,wherein the circuit is configured to charge and/or discharge the electrochemical cell in response to the control signal.

8. The system of claim 7, wherein the controller is configured to balance voltages or states of charge of the electrochemical cells of the pack.

9. The system of claim 7, wherein the circuit is configured to charge and/or discharge the electrochemical cell in response to the control signal and to automatically stop charging and/or discharging the electrochemical cell after a predetermined time period.

10. The system of claim 7, wherein the circuit is configured to charge and/or discharge the electrochemical cell for a predetermined time period in response to a refresh signal.

11. The system of claim 10, wherein the controller is configured to operate in at least a first power mode and a second power mode, wherein the controller uses less power in the second power mode than in the first power mode, wherein the controller is configured to generate the control signal when the controller is in the first power mode and not when the controller is in the second power mode, and wherein the system is configured to provide the refresh signal to the circuit when the controller is in the second power mode.

12. The system of claim 10, wherein the circuit is a first circuit coupled to a first electrochemical cell of the pack, and the system further comprises: a second circuit coupled to a second electrochemical cell of the pack and configured to charge and/or discharge the second electrochemical cell,wherein the first circuit is configured to receive the refresh signal from the second circuit.

13. The system of claim 7, wherein the control signal is a first control signal and the controller is further configured to generate a second control signal, and wherein the circuit is configured to stop charging and/or discharging the electrochemical cell in response to the second control signal.

14. The system of claim 1, wherein the circuit is a latching circuit configured to store a balancing command.

15. The system of claim 14, wherein the system is powered using a battery separate from the pack, and the circuit is configured such that if the battery is disconnected, the circuit will stop charging and/or discharging the battery within a predetermined amount of time.

16. The system of claim 1, wherein the charging and/or discharging is controlled at least in part by an application specific integrated circuit (ASIC), and the system is configured to repeatedly send a refresh signal to the ASIC so that the ASIC keeps charging and/or discharging one or more selected cells of the pack.

17. A system for charging and/or discharging electrochemical cells of a pack, the system comprising: a controller configured to generate a control signal; anda circuit coupled to an electrochemical cell of the pack, the circuit being configured to charge and/or discharge the electrochemical cell in response to the control signal and to automatically stop charging and/or discharging the electrochemical cell after a predetermined time period.

18. The system of claim 17, wherein the circuit comprises: a resistive element;a capacitor; anda transistor having a control terminal coupled to the resistive element and the capacitor.

19. The system of claim 18, further comprising: an amplifier coupled to the control terminal to amplify a signal provided by the resistive element and the capacitor.

20. The system of claim 17, wherein the circuit is a first circuit coupled to a first electrochemical cell of the pack, and the system further comprises: a second circuit coupled to a second electrochemical cell of the pack and configured to charge and/or discharge the second electrochemical cell in response to the control signal.

21. The system of claim 20, wherein the second circuit is connected to the first circuit to receive the control signal from the first circuit.

22. The system of claim 17, wherein the control signal is a first control signal and the controller is further configured to generate a second control signal, and wherein the circuit is configured to stop charging and/or discharging the electrochemical cell in response to the second control signal.

23. A system for charging and/or discharging electrochemical cells of a pack, the system comprising: a controller configured to generate at least one control signal; anda plurality of circuits individually coupled to respective electrochemical cells of the pack to charge and/or discharge the electrochemical cells in response to the at least one control signal,wherein the system is configured to draw no more than 100 mA on average from an auxiliary battery when in operation.

24. The system of claim 23, wherein the system is configured to draw no more than 50 mA on average from the auxiliary battery when in operation.

25. The system of claim 24, wherein the system is configured to draw no more than 2 mA on average from the auxiliary battery when in operation.

26. The system of claim 23, wherein the pack is configured to provide power to a motor of a vehicle.

27. The system of claim 26, wherein the controller is configured to generate the at least one control signal to control the plurality of circuits to charge and/or discharge the electrochemical cells of the pack at a plurality of times occurring throughout a period in which the vehicle is dormant.

28. The system of claim 23, wherein the system is configured to be powered by the auxiliary battery.

29. The system of claim 23, wherein the system is configured to be powered by the pack.

30. The system of claim 23, wherein the system is powered using no more than 100 mA on average.

31. The system of claim 30, wherein the system is powered using no more than 50 mA on average.

32. The system of claim 31, wherein the system is powered using no more than 2 mA on average.