Claims
- 1. A method of forming a wiring of a semiconductor device, comprising:
- the first step of forming a concave at a contact zone of a wiring zone of a resist pattern or an insulating layer formed on the semiconductor substrate; and
- the second step of forming an embedded metallic layer in said concave with the use of an electroless plating bath comprising: a metallic material containing metallic ions which is composed of silver nitrate; a reducing agent of said metallic ions which is composed of tartaric acid; a complexing agent of said metallic ions which is composed of ethylenediamine; and a pH control agent which is composed of tetramethylammoniumhydroxide.
- 2. A method of forming a wiring of a semiconductor device according to claim 1, further comprising, between said first and second steps, the intermediate layer forming step of successively forming, on the bottom of said concave, a resistance reducing layer for reducing the contact resistance of said embedded metallic layer, a barrier layer for preventing said embedded metallic layer from reacting, and a catalyzer layer for promoting the reaction of said metallic ions.
- 3. A method of forming a wiring of a semiconductor device according to claim 2, wherein
- said intermediate layer forming step comprises: the step of successively forming, inside of said concave and on said resist pattern or said insulating layer, said resistance reducing layer, said barrier layer and said catalyzer layer; and the step of removing, by a chemical and mechanical polishing method, said resistance reducing layer, said barrier layer and said catalyzer layer on said resist pattern or said insulating layer such that said resistance reducing layer, said barrier layer and said catalyzer layer are formed only on said bottom of said concave, and
- said second step comprises the step of selectively forming said embedded metallic layer on said catalyzer layer formed only on said bottom of said concave.
- 4. A method of forming a wiring of a semiconductor device according to claim 1, wherein said second step comprises: the step of forming, with the use of said electroless plating bath, a metallic layer inside of said concave and on said resist pattern or said insulating layer in its entirety; and the step of removing said metallic layer on said resist pattern or said insulating layer such that said embedded metallic layer is formed inside of said concave.
- 5. A method of forming a wiring of a semiconductor device according to claim 1, wherein said second step comprises: the step of forming, with the use of said electroless plating bath, a metallic layer inside of said concave and on said insulating layer in its entirety; and the step of removing, by a chemical and mechanical polishing method, said metallic layer on said insulating layer such that said embedded metallic layer is formed inside of said concave with the surface of said embedded metallic layer being flush with the surface of said insulating is layer.
- 6. A method of forming a wiring of a semiconductor device according to claim 1,
- further comprising, before said first step, the lower insulating layer forming step of forming, on said semiconductor substrate, a lower insulating layer having an embedded plug, and wherein
- said first step comprises:
- the step of forming said insulating layer on said lower insulating layer;
- the step of forming, on said insulating layer, a wiring zone forming resist pattern having an opening at the position thereof corresponding to said embedded plug; and
- the step of etching said insulating layer with said wiring zone forming resist pattern serving as a mask, thereby to form, in said insulating layer, said concave which will result in a wiring zone.
- 7. A method of forming a wiring of a semiconductor device according to claim 1,
- further comprising, before said first step, the lower insulating layer forming step of forming, on said semiconductor substrate, a lower insulating layer having an embedded plug, and wherein
- said first step comprises the step of forming, on said lower insulating layer, said resist pattern having, at the position thereof corresponding to said embedded plug, an opening which will result in said concave.
- 8. A method of forming a wiring of a semiconductor device according to claim 1, wherein said metallic material of said electroless plating bath comprises two or more types of metallic ions.
- 9. A method of forming a wiring of a semiconductor device according to claim 1, wherein said electroless plating bath further comprises at least one substance selected from the group consisting of: a pH buffer for restraining the plating solution from being lowered in pH, said buffer containing no metal in the chemical formula thereof; a promotor for restraining the plating speed from being lowered, said promotor containing no metal in the chemical formula thereof; a stabilizer for preventing said plating solution from being decomposed, said stabilizer containing no metal in the chemical formula thereof; and a surfactant for making the resulting plated layer fine in quality, said surfactant containing no metal in the chemical formula thereof.
Priority Claims (1)
Number |
Date |
Country |
Kind |
6-162030 |
Jul 1994 |
JPX |
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Parent Case Info
This is a divisional of application Ser. No. 08/502,175, filed Jul. 13, 1995, now U.S. Pat. No. 5,645,628.
US Referenced Citations (3)
Number |
Name |
Date |
Kind |
4469784 |
Heki et al. |
Sep 1984 |
|
5565235 |
Baudrand et al. |
Oct 1996 |
|
5580668 |
Kellam |
Dec 1996 |
|
Foreign Referenced Citations (1)
Number |
Date |
Country |
4-307735 |
Oct 1992 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
502175 |
Jul 1995 |
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