Patent Grant
12094397
This application claims the benefit of Republic of Korea Patent Application No. 10-2020-0170583, filed on Dec. 8, 2020, which is hereby incorporated by reference in its entirety.
The present disclosure relates to an electroluminescence display apparatus.
Electroluminescence display apparatuses include a plurality of pixels arranged as a matrix type, and a light emitting device included in each of the pixels emits light on the basis of image data to display luminance. To this end, each pixel may be supplied with a high level driving voltage and an initialization voltage.
Due to dynamic voltage (IR) drop occurring in a power line, a level of a high level driving voltage applied to a pixel varies based on a pixel position, causing an image quality deviation (i.e., a luminance deviation and a color deviation) between pixels.
Technology for predicting IR drop to perform compensation on the basis of a data voltage may be considered for reducing an image quality deviation between pixels, but because such compensation technology is based on prediction, the accuracy of compensation is low and the chip cost increases. Also, the compensation technology uses a method of lowering a data voltage with respect to a position at which luminance is the lowest, causing a reduction in screen luminance.
In a screen of each electroluminescence display apparatus, there is a problem where a luminance deviation between a region including a notch and a region including no notch occurs. Such a luminance deviation occurs due to a ripple deviation of the initialization voltage occurring between the regions.
To overcome the aforementioned problem of the related art, the present disclosure may provide an electroluminescence display apparatus for reducing an image quality deviation caused by IR drop occurring in a high level driving voltage power line.
Moreover, the present disclosure may provide an electroluminescence display apparatus for reducing an image quality deviation, caused by IR drop occurring in a high level driving voltage power line, and decreasing a luminance deviation caused by a ripple deviation of an initialization voltage occurring between a region including a notch and a region including no notch.
To achieve these objects and other advantages and in accordance with the purpose of the disclosure, as embodied and broadly described herein, an electroluminescence display apparatus includes a display panel including a plurality of pixels connected to a first power line, an EVDD power circuit converting a final feedback driving voltage input through a first input terminal thereof to output a high level driving voltage to a first position of the first power line through a first output terminal thereof, and a feedback control circuit receiving the high level driving voltage as a first feedback driving voltage, receiving a second feedback driving voltage from a second position of the first power line, and supplying the first input terminal of the EVDD power circuit with the final feedback driving voltage adjusted based on a first output contribution rate of the first feedback driving voltage and a second output contribution rate of the second feedback driving voltage, wherein dynamic voltage (IR) drop at the second position of the first power line is greater than IR drop at the first position of the first power line, and an output of the high level driving voltage increases in a vertical active period where a data application scan signal is supplied to the display panel.
In another aspect of the present disclosure, an electroluminescence display apparatus includes a display panel including a plurality of pixels connected to a first power line and a second power line, a common power circuit converting a final feedback driving voltage input through a first input terminal thereof to output a high level driving voltage to a first position of the first power line through a first output terminal thereof, receiving a feedback initialization voltage from a third position of the second power line through a second input terminal thereof, and converting the feedback initialization voltage to output an initialization voltage to a fourth position of the second power line through a second output terminal thereof, and a feedback control circuit receiving the high level driving voltage as a first feedback driving voltage, receiving a second feedback driving voltage from a second position of the first power line, and supplying the first input terminal of the common power circuit with the final feedback driving voltage adjusted based on a first output contribution rate of the first feedback driving voltage and a second output contribution rate of the second feedback driving voltage, wherein dynamic voltage (IR) drop at the second position of the first power line is greater than IR drop at the first position of the first power line, the number of horizontal-line pixels of the display panel corresponding to the third position is less than the number of horizontal-line pixels of the display panel corresponding to the fourth position, and an output of the high level driving voltage increases in a vertical active period where a data application scan signal is supplied to the display panel.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is only defined by scopes of claims.
The shapes, sizes, ratios, angles, numbers and the like disclosed in the drawings for description of various embodiments of the present disclosure to describe embodiments of the present disclosure are merely exemplary and the present disclosure is not limited thereto. Like reference numerals refer to like elements throughout. Throughout this specification, the same elements are denoted by the same reference numerals. As used herein, the terms “comprise”, “having,” “including” and the like suggest that other parts can be added unless the term “only” is used. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless context clearly indicates otherwise.
Elements in various embodiments of the present disclosure are to be interpreted as including margins of error even without explicit statements.
In describing a position relationship, for example, when a position relation between two parts is described as “on-”, “over-”, “under-”, and “next-”, one or more other parts may be disposed between the two parts unless “just” or “direct” is used.
It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.
Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
Referring to
The display panel PNL may include a plurality of signal lines (data lines and gate lines), which intersect with one another, and a pixel array configured with a plurality of pixels arranged as a matrix type. Each of the pixels PXL may include a light emitting device and a driving element. The light emitting device may be implemented with an organic light emitting diode or an inorganic light emitting diode, and the driving element may be implemented with a transistor based on silicon or oxide.
The display panel PNL may include an active area AA including the pixel array and a non-display area outside the active area AA. The pixel array may include a first power line which transfers a high level driving voltage EVDD to the pixels PXL and a second power line which transfers an initialization voltage Vini to the pixels PXL.
The pixels PXL may include a plurality of red pixels, a plurality of green pixels, a plurality of blue pixels, and a plurality of white pixels. The red pixel, the green pixel, the blue pixel, and the white pixel may configure one unit pixel for implementing a color. A color implemented in a unit pixel may be determined based on an emission rate of each of the red pixel, the green pixel, the blue pixel, and the white pixel. Also, the white pixel may be omitted in the unit pixel. A data line, a gate line, a first power line, and a second power line may be connected to each of the pixels PXL.
The panel driving circuit may include a data driver DDRV connected to the data lines of the display panel PNL and a gate driver GDRV connected to the gate lines of the display panel PNL.
The data driver DDRV may convert input image data, received from the timing control circuit TCON, into a data voltage Vdata and may supply the data voltage Vdata to the data lines. The data driver DDRV may output the data voltage Vdata by using a digital-to-analog converter (DAC) which converts the input image data into a gamma compensation voltage. The data driver DDRV may be manufactured as a chip type and may be directly mounted in the non-display area of the display panel PNL, and moreover, may be manufactured as an integrated circuit (IC) type and may be bonded to the display panel PNL through a conductive film.
The gate driver GDRV may generate a data application scan signal SCAN and may supply the data application scan signal SCAN to a plurality of first gate lines. The data application scan signal SCAN may be selected pixels PXL, which are to be charged with the data voltage Vdata, by horizontal pixel line units. When an emission signal EM is further needed based on a pixel PXL structure, the gate driver GDRV may further generate the emission signal EM and may supply the emission signal EM to a plurality of second gate lines. The emission signal EM may determine an emission period of the pixel PXL in one frame.
The gate driver GDRV may be directly provided in the non-display area of the display panel PNL along with the pixel array through a gate-driver in panel (GIP) process, and moreover, may be manufactured as an IC type and may be bonded to the display panel PNL through a conductive film.
The timing control circuit TCON may receive digital data of an input image and a timing signal synchronized therewith from a host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The host system may be one of a television (TV) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system, but is not limited thereto.
The timing control circuit TCON may generate a data timing control signal for controlling an operation timing of the data driver DDRV and a gate timing control signal for controlling an operation timing of the gate driver GDRV, on the basis of the timing signal Vsync, Hsync, and DE. The timing control circuit TCON may further generate the MUX control signal used to compensate for an image quality deviation on the basis of the timing signal Vsync, Hsync, and DE (see
The feedback control circuit FBCON may receive a first feedback driving voltage at a first position, at which IR drop is relatively small, of a first power line, receive a second feedback driving voltage at a second position, at which IR drop is relatively large, of the first power line, and appropriately process the first and second feedback driving voltages to output a final feedback driving voltage corresponding to a third position of the first power line. Here, the third position may be between the first position and the second position, and IR drop at the third position may be greater than IR drop at the first position and less than IR drop at the second position.
The power generating circuit PMIC may include an EVDD power circuit implemented with a DC-DC converter. The EVDD power circuit may convert the final feedback driving voltage input from the feedback control circuit FBCON to output the high level driving voltage EVDD to the first position of the first power line. Particularly, in order to decrease an image quality deviation caused by IR drop occurring in the first power line, the power generating circuit PMIC may progressively increase an output of the high level driving voltage EVDD in a vertical active period where the data application scan signal SCAN is supplied, and thus, the final feedback driving voltage may be shifted to a certain target voltage level or may be within a target voltage range including the certain target voltage level.
The power generating circuit PMIC may further include a Vini power circuit implemented with a DC-DC converter. The Vini power circuit may receive a feedback initialization voltage from a third position of the second power line and may convert the feedback initialization voltage to output the initialization voltage Vini to a fourth position of the second power line. One of the third position and the fourth position may correspond to a region including a notch, and the other of the third position and the fourth position may correspond to a region including no notch. Therefore, a luminance deviation caused by a ripple deviation of the initialization voltage occurring between the region including a notch and the region including no notch may be reduced.
In the power generating circuit PMIC, the EVDD power circuit and the Vini power circuit may be independently configured, or may be integrated.
The timing control circuit TCON, the feedback control circuit FBCON, and the power generating circuit PMIC may be mounted on a control board CBRD, but are not limited thereto. The timing control circuit TCON and the data driver DDRV may be provided as one chip and may be mounted on the display panel PNL, and some elements of the feedback control circuit FBCON may be mounted on the display panel PNL.
Referring to
The OLED may be a light emitting device which emits light with a driving current. An anode electrode of the OLED may be connected to a node N4, and a cathode electrode of the OLED may be connected to an input terminal of a low level driving voltage EVSS. An organic compound layer may be provided between the anode electrode and the cathode electrode of the OLED.
A driving TFT DT may be a driving element which adjusts a driving current flowing in the OLED on the basis of a gate-source voltage thereof. The driving TFT DT may include a gate electrode connected to a node N2, a first electrode connected to a node N1, and a second electrode connected to a node N3.
The first switch TFT T1 may be a switch element which is connected between a data line 14 and the node N1 and is turned on based on an nth scan signal SCAN(n). A gate electrode of the first switch TFT T1 may be connected to an nth first gate line 15a(n) to which the nth scan signal SCAN (n) is applied, a first electrode of the first switch TFT T1 may be connected to the data line 14, and a second electrode of the first switch TFT T1 may be connected to the node N1.
The second switch TFT T2 may be a switch element which is connected between a first power line 17 and the node N1 and is turned on based on an nth emission signal EM(n). A gate electrode of the second switch TFT T2 may be connected to an nth second gate line 15b(n) to which the nth emission signal EM(n) is applied, a first electrode of the second switch TFT T2 may be connected to the first power line 17, and a second electrode of the second switch TFT T2 may be connected to the node N1.
The third switch TFT T3 may be a switch element which is connected between the node N2 and the node N3 and is turned on based on the nth scan signal SCAN(n). A gate electrode of the third switch TFT T3 may be connected to the nth first gate line 15a(n) to which the nth scan signal SCAN (n) is applied, a first electrode of the third switch TFT T3 may be connected to the node N3, and a second electrode of the third switch TFT T3 may be connected to the node N2.
The fourth switch TFT T4 may be a switch element which is connected between the node N2 and a second power line 16 and is turned on based on an n−1th scan signal SCAN(n−1). A gate electrode of the fourth switch TFT T4 may be connected to an n-first gate line 15a(n−1) to which the n−1th scan signal SCAN(n−1) is applied, a first electrode of the fourth switch TFT T4 may be connected to the node N2, and a second electrode of the fourth switch TFT T4 may be connected to the second power line 16.
The fifth switch TFT T5 may be a switch element which is connected between the node N3 and the node N4 and is turned on based on the nth emission signal EM(n). A gate electrode of the fifth switch TFT T5 may be connected to the nth second gate line 15b(n) to which the nth emission signal EM(n) is applied, a first electrode of the fifth switch TFT T5 may be connected to the node N3, and a second electrode of the fifth switch TFT T5 may be connected to the node N4.
The sixth switch TFT T6 may be a switch element which is connected between the node N4 and the second power line 16 and is turned on based on the nth scan signal SCAN(n). A gate electrode of the sixth switch TFT T6 may be connected to the nth first gate line 15a(n) to which the nth scan signal SCAN(n) is applied, a first electrode of the sixth switch TFT T6 may be connected to the node N4, and a second electrode of the sixth switch TFT T6 may be connected to the second power line 16.
The storage capacitor Cst may be connected between the first power line 17 and the node N2.
The pixel PXL of
In the initialization period, the node N2 may be reset to an initialization voltage Vini, and voltages of floated nodes N1 and N3 may be voltages which are lower than a high level driving voltage EVDD.
In the sampling period, a threshold voltage Vth of the driving TFT DT may be sampled and may be stored in the node N2 and the node N3. During the sampling period, a gate-source voltage of the driving TFT DT may be a threshold voltage of the driving TFT DT.
In the emission period, the OLED may emit light with a driving current which flows in the driving TFT DT.
In the PWM driving period, the light emission of the OLED may stop. In one frame, an emission duty may be determined based on a length of the PWM driving period. When the OLED is repeatedly turned on or off at a certain emission duty ratio, an afterimage may be minimized in implementing a low gray level.
The technical spirit of the present disclosure is not limited to the pixel PXL structure of
The technical spirit of the present disclosure may reduce an image quality deviation caused by IR drop occurring in a high level driving voltage power line (i.e., the first power line). Furthermore, the technical spirit of the present disclosure may further decrease a luminance deviation caused by a ripple deviation of the initialization voltage Vini occurring between a region including a notch and a region including no notch. The technical spirit of the present disclosure may be implemented by a compensation system according to various embodiments which will be described below.
First to fourth embodiments may reduce an image quality deviation caused by IR drop, and fifth to ninth embodiments may decrease all of an image quality deviation caused by the IR drop of the high level driving voltage and the luminance deviation caused by the ripple deviation of the initialization voltage.
Referring to
A plurality of pixels connected to a first power line may be included in the display panel PNL, and each of the pixels may be supplied with a high level driving voltage EVDD-OUT through the first power line.
The EVDD power circuit may convert a final feedback driving voltage EVDD-FB input through a first input terminal TER1 to output the high level driving voltage EVDD-OUT to a first position TI of the first power line through a first output terminal TER2.
The EVDD power circuit may progressively increase an output of the high level driving voltage EVDD-OUT so that the final feedback driving voltage EVDD-FB has a certain target voltage, in a vertical active period Vactive where a data application scan signal SCAN is supplied. Therefore, in the vertical active period Vactive, a first feedback driving voltage EVDD-FB1 may be shifted in a direction increasing from the target voltage, and a second feedback driving voltage EVDD-FB2 may be shifted in a direction increasing toward the target voltage. In addition, “Vblank” in
The feedback control circuit FBCON may oppositely change a first output contribution rate of the first feedback driving voltage EVDD-FB1 and a second output contribution rate of the second feedback driving voltage EVDD-FB2 so that the final feedback driving voltage EVDD-FB has the certain target voltage. In other words, the feedback control circuit FBCON may change the first output contribution rate of the first feedback driving voltage EVDD-FB1 in a direction decreasing from 100% to 0% and may change the second output contribution rate of the second feedback driving voltage EVDD-FB2 in a direction increasing from 0% to 100%. The final feedback driving voltage EVDD-FB may maintain the target voltage on the basis of the first output contribution rate of the first feedback driving voltage EVDD-FB1 and the second output contribution rate of the second feedback driving voltage EVDD-FB2, and thus, an image quality deviation caused by IR drop may be effectively reduced.
The feedback control circuit FBCON may receive the high level driving voltage EVDD-OUT as the first feedback driving voltage EVDD-FB1 and may receive the second feedback driving voltage EVDD-FB2 from a second position TO of a first power line, and then, may supply the first input terminal TER1 of the EVDD power circuit with the final feedback driving voltage EVDD-FB adjusted based on the first output contribution rate of the first feedback driving voltage EVDD-FB1 and the second output contribution rate of the second feedback driving voltage EVDD-FB2. Here, IR drop at the second position of the first power line may be greater than IR drop at the first position of the first power line. In other words, in magnitude of IR drop in the first power line, the IR drop may be the smallest at the first position and the IR drop may be the largest at the second position.
The feedback control circuit FBCON may include a control signal generating circuit SWCON which generates a first output control signal CTR1 for determining the first output contribution rate and a second output control signal CTR2 for determining the second output contribution rate, a first buffer BUF1 which receives the first feedback driving voltage EVDD-FB1, a second buffer BUF2 which receives the second feedback driving voltage EVDD-FB2, a first MOS transistor MOS1 which connects an output of the first buffer BUF1 to the first input terminal TER1 of the EVDD power circuit on the basis of an on rate thereof controlled according to the first output control signal CTR1, and a second MOS transistor MOS2 which connects an output of the second buffer BUF2 to the first input terminal TER1 of the EVDD power circuit on the basis of an on rate thereof controlled according to the second output control signal CTR2.
The first buffer BUF1 may prevent or at least reduce a reverse current occurring in the first MOS transistor MOS1 from being applied to the display panel PNL. Likewise, the second buffer BUF2 may prevent or at least reduce a reverse current occurring in the second MOS transistor MOS2 from being applied to the display panel PNL.
It is illustrated in
In an initial period of the vertical active period Vactive, the first MOS transistor MOS1 may be turned on by 100% and the final feedback driving voltage EVDD-FB may be the first final feedback driving voltage EVDD-FB1 which is a target voltage (for example, 4.6 V), and in a last period of the vertical active period Vactive, the second MOS transistor MOS2 may be turned on by 100% and the final feedback driving voltage EVDD-FB may be the second final feedback driving voltage EVDD-FB2 which is a target voltage (for example, 4.6 V). Also, in a middle period of the vertical active period Vactive, the first MOS transistor MOS1 may be turned on by A % (where A is a natural number smaller than 100), the second MOS transistor MOS2 may be turned on by (100−A) %, and the final feedback driving voltage EVDD-FB may be a target voltage (for example, 4.6 V) between the first final feedback driving voltage EVDD-FB1 and the second final feedback driving voltage EVDD-FB2.
In order to progressively increase the high level driving voltage EVDD-OUT, the EVDD power circuit may include a first voltage division resistor string R1 and R2 connected to the first input terminal TER1 and a first converting circuit which DC-DC converts the final feedback driving voltage EVDD-FB divided by the first voltage division resistor string R1 and R2 to output the high level driving voltage EVDD-OUT capable of compensating for an image quality deviation caused by IR drop. The EVDD power circuit may be implemented with a first DC-DC converter including a first converting circuit.
It is illustrated that the first DC-DC converter is a buck converter, but the inventive concept is not limited thereto and the first DC-DC converter may be replaced with another type of converter such as a boost converter.
The first DC-DC converter may include a first amplifier AMP1 which compares a reference voltage REF with the final feedback driving voltage EVDD-FB divided by a first voltage division node Nx of the first voltage division resistor string R1 and R2, a second amplifier AMP2 which compares an output of the first amplifier AMP1 with a ramp waveform RAMP to generate a PWM output waveform, a first controller CONL which outputs a first switch control signal and a second switch control signal having opposite phases on the basis of the PWM output waveform, a first output switch S1 which is connected between a high level source voltage VI and a first output node Na, a second output switch S2 which is connected between the first output node Na and a low level source voltage VSS, a first inductor L which is connected between the first output node Na and a first output terminal TER2, and a first capacitor C which is connected between the first output terminal TER2 and the low level source voltage VSS.
As in
The high level driving voltage EVDD-OUT may be applied to all horizontal pixel lines at a certain level by using a compensation mechanism during the vertical active period Vactive, thereby preventing or at least reducing image quality from being degraded by IR drop.
Referring to
The display panel PNL and the EVDD power circuit of
In detail, the feedback control circuit FBCON may receive a high level driving voltage EVDD-OUT as a first feedback driving voltage EVDD-FB1 and may receive a second feedback driving voltage EVDD-FB2 from a second position TO of a first power line, and then, may supply a first input terminal TER1 of the EVDD power circuit with a final feedback driving voltage EVDD-FB adjusted based on a first output contribution rate of the first feedback driving voltage EVDD-FB1 and a second output contribution rate of the second feedback driving voltage EVDD-FB2. Here, IR drop at the second position of the first power line may be greater than IR drop at the first position of the first power line. In other words, in magnitude of IR drop in the first power line, the IR drop may be the smallest at the first position and the IR drop may be the largest at the second position.
In a vertical active period Vactive where a data application scan signal SCAN is supplied, as in
Referring to
To this end, as in
The first buffer BUF1 may prevent or at least reduce a reverse current occurring in the first MOS transistor MOS1 from being applied to the display panel PNL. Likewise, the second buffer BUF2 may prevent or at least reduce a reverse current occurring in the second MOS transistor MOS2 from being applied to the display panel PNL.
It is illustrated in
Referring to
The display panel PNL and the EVDD power circuit of
In detail, the feedback control circuit FBCON may receive a high level driving voltage EVDD-OUT as a first feedback driving voltage EVDD-FB1 and may receive a second feedback driving voltage EVDD-FB2 from a second position TO of a first power line, and then, may supply a first input terminal TER1 of the EVDD power circuit with a final feedback driving voltage EVDD-FB adjusted based on a first output contribution rate of the first feedback driving voltage EVDD-FB1 and a second output contribution rate of the second feedback driving voltage EVDD-FB2. Here, IR drop at the second position of the first power line may be greater than IR drop at the first position of the first power line. In other words, in magnitude of IR drop in the first power line, the IR drop may be the smallest at the first position and the IR drop may be the largest at the second position.
In a vertical active period Vactive where a data application scan signal SCAN is supplied, as in
In the vertical active period Vactive, the feedback control circuit FBCON may change the first feedback driving voltage EVDD-FB1 in a direction increasing from a target level and may change the second feedback driving voltage EVDD-FB2 in a direction increasing toward the target level. At this time, the feedback control circuit FBCON may oppositely change the first output contribution rate of the first feedback driving voltage EVDD-FB1 and the second output contribution rate of the second feedback driving voltage EVDD-FB2. In other words, the feedback control circuit FBCON may change the first output contribution rate of the first feedback driving voltage EVDD-FB1 in a direction decreasing from 100% to 0% and may change the second output contribution rate of the second feedback driving voltage EVDD-FB2 in a direction increasing from 0% to 100%.
To this end, as in
It is illustrated in
Referring to
The display panel PNL and the EVDD power circuit of
In detail, the feedback control circuit FBCON may receive a high level driving voltage EVDD-OUT as a first feedback driving voltage EVDD-FB1 and may receive a second feedback driving voltage EVDD-FB2 from a second position TO of a first power line, and then, may supply a first input terminal TER1 of the EVDD power circuit with a final feedback driving voltage EVDD-FB adjusted based on a first output contribution rate of the first feedback driving voltage EVDD-FB1 and a second output contribution rate of the second feedback driving voltage EVDD-FB2. Here, IR drop at the second position of the first power line may be greater than IR drop at the first position of the first power line. In other words, in magnitude of IR drop in the first power line, the IR drop may be the smallest at the first position and the IR drop may be the largest at the second position.
In a vertical active period Vactive where a data application scan signal SCAN is supplied, as in
In the vertical active period Vactive, the feedback control circuit FBCON may change the first feedback driving voltage EVDD-FB1 in a direction increasing from a target level and may change the second feedback driving voltage EVDD-FB2 in a direction increasing toward the target level. At this time, the feedback control circuit FBCON may oppositely change the first output contribution rate of the first feedback driving voltage EVDD-FB1 and the second output contribution rate of the second feedback driving voltage EVDD-FB2. In other words, the feedback control circuit FBCON may change the first output contribution rate of the first feedback driving voltage EVDD-FB1 in a direction decreasing from 100% to 0% and may change the second output contribution rate of the second feedback driving voltage EVDD-FB2 in a direction increasing from 0% to 100%.
To this end, as in
It is illustrated in
Referring to
The first area A may include fewer pixels included in one horizontal pixel line than the second area B. Due to such a pixel number difference, a total current corresponding to one horizontal pixel line of the first area A may be less than a total current corresponding to one horizontal pixel line of the second area B. Therefore, a ripple magnitude of an initialization voltage Vini supplied to one horizontal pixel line of the first area A may be less than a ripple magnitude of the initialization voltage Vini supplied to one horizontal pixel line of the second area B. Also, due to such a ripple deviation, the initialization voltage Vini in the second area B may be “ΔV” higher than the initialization voltage Vini in the first area A, causing a luminance deviation between the first area A and the second area B.
In order to compensate for an image quality deviation caused by the IR drop of a high level driving voltage and to further compensate for a luminance deviation caused by a ripple deviation of the above-described initialization voltage, the electroluminescence display apparatus according to the present disclosure may use a compensation system according to fifth to eighth embodiments.
The compensation system according to the fifth embodiment illustrated in
In
A Vini power circuit may include a second input terminal TER3 and a second output terminal TER4. The Vini power circuit may receive a feedback initialization voltage Vini-FB from a third position TO1 of a second power line through the second input terminal TER3 and may convert the feedback initialization voltage Vini-FB to output the initialization voltage Vini-OUT to a fourth position TI1 of the second power line through the second output terminal TER4.
Here, the third position TO1 may correspond to the first area A of
The Vini power circuit may control the initialization voltage Vini-OUT which is to be supplied to the fourth position TH, with respect to the feedback initialization voltage Vini-FB corresponding to the third position TO1.
The Vini power circuit may include a second voltage division resistor string R3 and R4 connected to the second input terminal TER3 and a second converting circuit which DC-DC converts the feedback initialization voltage Vini-FB divided by the second voltage division resistor string R3 and R4 to output the initialization voltage Vini-OUT capable of compensating for a luminance deviation caused by a ripple deviation.
It is illustrated that the second DC-DC converter is a buck converter, but the inventive concept is not limited thereto and the second DC-DC converter may be replaced with another type of converter such as a boost converter.
The second DC-DC converter may include a third amplifier AMP3 which compares a reference voltage REF with the feedback initialization voltage Vini-FB divided by a second voltage division node Ny of the second voltage division resistor string R3 and R4, a fourth amplifier AMP4 which compares an output of the third amplifier AMP3 with a ramp waveform RAMP to generate a PWM1 output waveform, a second controller CONL1 which outputs a third switch control signal and a fourth switch control signal having opposite phases on the basis of the PWM1 output waveform, a third output switch S3 which is connected between a high level source voltage VI and a second output node Nb, a fourth output switch S4 which is connected between the second output node Nb and a low level source voltage VSS, a second inductor L1 which is connected between the second output node Nb and the second output terminal TER4, and a second capacitor C1 which is connected between the second output terminal TER4 and the low level source voltage VSS.
The Vini power circuit may receive the feedback initialization voltage Vini-FB through the second input terminal TER3 to output the initialization voltage Vini-OUT through the second output terminal TER4. When the feedback initialization voltage Vini-FB is lower than a target initialization voltage, the Vini power circuit may increase the initialization voltage Vini-OUT, and when the feedback initialization voltage Vini-FB is higher than the target initialization voltage, the Vini power circuit may decrease the initialization voltage Vini-OUT. Based on such a voltage feedback operation, the feedback initialization voltage Vini-FB may maintain a predetermined or certain target initialization voltage in the vertical active period, thereby reducing a luminance deviation caused by a ripple deviation between a notch region and a non-notch region.
For example, when a relatively large ripple occurs in an initialization voltage at the third position TO1, the feedback initialization voltage Vini-FB may increase over time, and thus, a negative (−) input voltage of the third amplifier AMP3 may increase. On the other hand, an output of the third amplifier AMP3 and a positive (+) input of the fourth amplifier AMP4 may be lowered. Therefore, an on duty period of a PMW1 signal may be shortened over time, and an operation duty of the second DC-DC converter may be reduced by the third output switch S3 and the fourth output switch S4, whereby the initialization voltage Vini-OUT may be lowered. As described above, the initialization voltage Vini-OUT may be adjusted so that the feedback initialization voltage is a target initialization voltage.
Referring to
The compensation system according to the ninth embodiment may include a display panel PNL, a common power circuit, and a feedback control circuit FBCON.
A plurality of pixels connected to a first power line and a second power line may be included in the display panel PNL, and each of the pixels may be supplied with a high level driving voltage EVDD-OUT through the first power line and may be supplied with the initialization voltage Vini-OUT through the second power line.
The common power circuit may convert a final feedback driving voltage EVDD-FB input through a first input terminal TER1 thereof to output the high level driving voltage EVDD-OUT to a first position TI of the first power line through a first output terminal TER2 thereof. Also, the common power circuit may receive a feedback initialization voltage Vini-FB from a third position TO1 of the second power line through a second input terminal TER3 thereof and may convert the feedback initialization voltage Vini-FB to output the initialization voltage Vini-OUT to a fourth position TI1 of the second power line through a second output terminal TER4 thereof.
The feedback control circuit FBCON may receive a high level driving voltage EVDD-OUT as a first feedback driving voltage EVDD-FB1 and may receive a second feedback driving voltage EVDD-FB2 from a second position TO of the first power line, and then, may supply the first input terminal TER1 of the common power circuit with a final feedback driving voltage EVDD-FB adjusted based on a first output contribution rate of the first feedback driving voltage EVDD-FB1 and a second output contribution rate of the second feedback driving voltage EVDD-FB2. Here, IR drop at the second position of the first power line may be greater than IR drop at the first position of the first power line. In other words, in magnitude of IR drop in the first power line, the IR drop may be the smallest at the first position and the IR drop may be the largest at the second position.
In a vertical active period Vactive where a data application scan signal SCAN is supplied, as in
As described above, in the vertical active period Vactive where the data application scan signal SCAN is supplied, the final feedback driving voltage EVDD-FB may maintain the target voltage on the basis of the first output contribution rate of the first feedback driving voltage EVDD-FB1 and the second output contribution rate of the second feedback driving voltage EVDD-FB2, and thus, an image quality deviation caused by IR drop may be effectively reduced.
Moreover, the third position TO1 may correspond to the first area A of
The common power circuit may include a first voltage division resistor string R1 and R2 connected to the first input terminal TER1, a second voltage division resistor string R3 and R4 connected to the second input terminal TER3, a converting circuit CIRC which selectively converts the final feedback driving voltage EVDD-FB and the feedback initialization voltage Vini-FB to selectively output the high level driving voltage EVDD-OUT and the initialization voltage Vini-OUT, a first switching circuit MUX1 which selectively connects the first voltage division resistor string R1 and R2 and the second voltage division resistor string R3 and R4 to the converting circuit CIRC on the basis of a MUX control signal MUX-CON, and a second switching circuit MUX2 which selectively connects an output terminal Nc of the converting circuit CIRC to the first output terminal TER2 and the second output terminal TER4 on the basis of the MUX control signal MUX-CON.
As in
In the first period, the first switching circuit MUX1 may connect the first voltage division resistor string R1 and R2 to the converting circuit CIRC on the basis of the MUX control signal MUX-CON having the first level LV1, and the second switching circuit MUX2 may connect the output terminal Nc of the converting circuit CIRC to the first output terminal TER2 on the basis of the MUX control signal MUX-CON having the first level LV1.
In the second period, the first switching circuit MUX1 may connect the second voltage division resistor string R3 and R4 to the converting circuit CIRC on the basis of the MUX control signal MUX-CON having the second level LV2, and the second switching circuit MUX2 may connect the output terminal Nc of the converting circuit CIRC to the second output terminal TER4 on the basis of the MUX control signal MUX-CON having the second level LV2.
The first switching circuit MUX1 may include a first terminal 1a connected to a first voltage division node Nx of the first voltage division resistor string R1 and R2, a second terminal 1b connected to a second voltage division node Ny of the second voltage division resistor string R3 and R4, and a third terminal which selectively connects the first terminal 1a and the second terminal 1b to the converting circuit CIRC on the basis of the MUX control signal MUX-CON.
The second switching circuit MUX2 may include a first terminal 2a connected to the first output terminal TER2, a second terminal 2b connected to the second output terminal TER4, and a third terminal which selectively connects the first terminal 2a and the second terminal 2b to the output terminal Nc of the converting circuit CIRC on the basis of the MUX control signal MUX-CON.
The converting circuit CIRC may include a first amplifier AMP1 which compares a reference voltage REF with the final feedback driving voltage EVDD-FB divided by the first voltage division node Nx of the first voltage division resistor string R1 and R2 or the feedback initialization voltage Vini-FB divided by the second voltage division node Ny of the second voltage division resistor string R3 and R4, a second amplifier AMP2 which compares an output of the first amplifier AMP1 with a ramp waveform RAMP to generate a PWM output waveform, a first controller CONL which outputs a first switch control signal and a second switch control signal having opposite phases on the basis of the PWM output waveform, a first output switch S1 which is connected between a high level source voltage VI and the first output node Na, a second output switch S2 which is connected between the first output node Na and a low level source voltage VSS, a first inductor L which is connected between the first output node Na and the output terminal Nc, and a first capacitor C which is connected between the output terminal Nc and the low level source voltage VSS.
In the vertical active period Vactive, the feedback control circuit FBCON may change the first feedback driving voltage EVDD-FB1 in a direction increasing from a target level and may change the second feedback driving voltage EVDD-FB2 in a direction increasing toward the target level. At this time, the feedback control circuit FBCON may oppositely change the first output contribution rate of the first feedback driving voltage EVDD-FB1 and the second output contribution rate of the second feedback driving voltage EVDD-FB2. In other words, the feedback control circuit FBCON may change the first output contribution rate of the first feedback driving voltage EVDD-FB1 in a direction decreasing from 100% to 0% and may change the second output contribution rate of the second feedback driving voltage EVDD-FB2 in a direction increasing from 0% to 100%.
A configuration of the feedback control circuit FBCON may be substantially the same as the descriptions of the first to fourth embodiments.
The embodiments of the present disclosure may realize the following effects.
According to the embodiments of the present disclosure, an image quality deviation caused by IR drop occurring in a high level driving voltage power line may be reduced.
Moreover, according to the embodiments of the present disclosure, an image quality deviation caused by IR drop occurring in the high level driving voltage power line and a luminance deviation caused by a ripple deviation of an initialization voltage occurring between a region including a notch and a region including no notch may be reduced.
The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the following claims.
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| 10-2020-0170583 | Dec 2020 | KR | national |
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| 20220180800 A1 | Jun 2022 | US |
