Patent Grant
10438536
This Application claims priority to Chinese Patent Application No. CN201710642948.0, filed on Jul. 31, 2017, the content of which is incorporated by reference in the entirety.
The present disclosure relates to the field of display technologies, and particularly to an electroluminescent display panel, a display device and a method for driving the same.
Having advantages like fast response speed, wide color gamut, wide angle of view, high brightness and light weight, etc., organic light emitting diode (OLED) displays have attracted much attention, and have been widely used in the field of light emitting technologies. However, since the OLED display is a display driven by current, stable current is needed to drive the display to emit light. Because of process factors, device ageing, etc. OLEDS are prone to instability from drifts of threshold voltage (Vth) of a drive transistor of a pixel circuit, thereby causing non-uniform display and an afterimage.
To solve this problem, people have applied a pixel circuit with a compensation function in general, to compensate for the threshold voltage; for example, a pixel circuit as illustrated in
Embodiments of the present disclosure provide an electroluminescent display panel, a display device, and a method for driving the same.
An embodiment of the present disclosure provides an electroluminescent display panel, including a plurality of pixel circuits arranged in an array, wherein the plurality of pixel circuits each includes a node initialization module and an anode reset module; wherein a connection passage is arranged between every two adjacent pixel circuits of each column of the plurality of pixel circuits; and wherein the connection passage is configured to provide a reference signal to either an anode reset module or a node initialization module of one of the every two adjacent pixel circuits.
In another aspect, an embodiment of the present disclosure further provides a display device, including the electroluminescent display panel above according to the embodiment of the present disclosure.
In still another aspect, an embodiment of the present disclosure further provides a method for driving the electroluminescent display panel above according to the embodiment of the present disclosure, including: providing, by the connection passage, the node initialization module of the one of the every two adjacent pixel circuits with the reference signal, in an initialization stage of the one of the every two adjacent pixel circuits; or, providing, by the connection passage, the anode reset module of the one of the every two adjacent pixel circuits with the reference signal, in a data writing stage of the one of the every two adjacent pixel circuits.
The particular embodiments of the electroluminescent display panel, the display device and the method for driving the same according to the embodiments of the disclosure will be described below in details with reference to the drawings. It shall be noted that the embodiments described below are only a part but not all of the embodiments of the disclosure. Based upon the embodiments here of the disclosure, all the other embodiments which can occur to those skilled in the art without any inventive effort shall fall into the scope of the disclosure.
As a result of a simulation on the pixel circuit illustrated in
As can be apparent from Table 1 above, the potential of the second node N2 in the n-th frame is different from the potential of the second node N2 in the (n+1)-th frame in the initialization stage. This is because the first node N1 is switched to the potential −3V in the n-th frame from 3.44V, and the first node N1 is switched to the potential −3V in the (n+1)-th frame from 1.5V, in the initialization stage. And there is a parasitic capacitance between the first node N1 and the second node N2 in the pixel circuit, and the second node N2 is floating in the initialization stage. Therefore there is such a different change in voltage ΔV of the first node N1 that the potential of the second node N2 in the n-th frame is different from the potential of the second node N2 in the (n+1)-th frame in the initialization stage, so that the potential of the first node N1 in the n-th frame is different from the potential of the first node N1 in the (n+1)-th frame in the data writing stage, thus resulting in such a problem that the brightness of the n-th frame is different from the brightness of the (n+1)-th frame.
In view of this, an embodiment of the disclosure provides an electroluminescent display panel. By resetting the potentials of both the first node N1 and the second node N2 in the initialization stage, the problem of different brightness arising from their difference in potential due to the parasitic capacitance between them is avoided. Moreover, by arranging a connection passage between every two adjacent pixel circuits of each column of the plurality of pixel circuits, a reference signal is provided for an adjacent pixel circuit, so that the number of signal ports can be reduced and the wiring space can be saved.
In one or more embodiments, the electroluminescent display panel according to the embodiment of the disclosure, as illustrated in
In the electroluminescent display panel above according to the embodiment of the disclosure, by arranging a connection passage between every two adjacent pixel circuits of each column of the plurality of pixel circuits, not only key nodes can be initialized via a node initialization module, thereby avoiding the problem of threshold voltage being differently grabbed due to a voltage jump and effectively preventing the afterimage from occurring as a result of the deviating threshold voltage of the drive transistor, but also a reference signal can be provided for either an anode reset module 102 or a node initialization module 101 of an adjacent pixel circuit, thereby reducing the number of signal ports and saving wiring space.
In a particular implementation, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
An anode reset module 102 of the each pixel circuit includes a first terminal electrically connected with a second scan signal terminal of the each pixel circuit, a second terminal electrically connected with a third node N3 of the each pixel circuit, and a third terminal used for receiving a reference signal; and the anode reset module 102 is configured to be controlled by a second scan signal input from the second scan signal terminal of the each pixel circuit to transmit the reference signal received by the third terminal of the anode reset module 102 to the third node N3 of the each pixel circuit.
The connection passage is configured to provide a reference signal to a third terminal of the anode reset module 102 or a fifth terminal of the node initialization module 101 of the one of the every two adjacent pixel circuits.
In a particular implementation, as illustrated in
A data writing module 103 of the pixel circuit P1 includes a first terminal electrically connected with a second scan signal terminal S2 of the pixel circuit P1, a second terminal electrically connected with a data signal terminal Vdata of the pixel circuit P1, a third terminal electrically connected with a second node N2 of the pixel circuit P1, a fourth terminal electrically connected with a first node N1 of the pixel circuit P1, and a fifth terminal electrically connected with a fourth node N4 of the pixel circuit P1; and the data writing module 103 of the pixel circuit P1 is configured to be controlled by a second scan signal input from the second scan signal terminal S2 of the pixel circuit P1 to transmit a data signal input from the data signal terminal Vdata of the pixel circuit P1 to the second node N2 of the pixel circuit P1, and to provide an electric potential at the fourth node N4 of the pixel circuit P1 to the first node N1 of the pixel circuit P1.
A light emitting control module 104 of the pixel circuit P1 includes a first terminal electrically connected with a light emitting control signal terminal EMIT1 of the pixel circuit P1, a second terminal electrically connected with a first voltage signal terminal PVDD of the pixel circuit P1, a third terminal electrically connected with the second node N2 of the pixel circuit P1, a fourth terminal electrically connected with the fourth node N4 of the pixel circuit P1, and a fifth terminal electrically connected with a third node N3 of the pixel circuit P1; and the light emitting control module 104 of the pixel circuit P1 is configured to be controlled by a light emitting control signal input from the light emitting control signal terminal EMIT1 of the pixel circuit P1 to transmit a first voltage signal input from the first voltage signal terminal PVDD of the pixel circuit P1 to the second node N2 of the pixel circuit P1, and to provide the electric potential at the fourth node N4 of the pixel circuit P1 to the third node N3 of the pixel circuit P1.
A drive control module 105 of the pixel circuit P1 includes a first terminal electrically connected with the first node N1 of the pixel circuit P1, a second terminal electrically connected with the first voltage signal terminal PVDD of the pixel circuit P1, a third terminal electrically connected with the second node N2 of the pixel circuit P1, and a fourth terminal electrically connected with the fourth node N4 of the pixel circuit P1; and the drive control module 105 of the pixel circuit P1 is configured to be controlled by the first voltage signal input from the first voltage signal terminal PVDD of the pixel circuit P1 to maintain an electric potential at the first node N1 of the pixel circuit P1, and to be controlled by the first node N1 of the pixel circuit P1 to connect the second node N2 of the pixel circuit P1 with the fourth node N4 of the pixel circuit P1.
A light emitting diode 106 of the pixel circuit P1 includes a first terminal electrically connected with the third node N3 of the pixel circuit P1, and a second terminal electrically connected with a second voltage signal terminal PVEE of the pixel circuit P1.
In one or more embodiments, a structure of a pixel circuit in the electroluminescent display panel illustrated in
As apparent from Table 2 above, the potential of the second node N2 in the n-th frame is substantially the same as the potential of the second node N2 in the (n+1)-th frame in the initialization stage. The first node N1 is switched to the potential −3V in the n-th frame from 3.44V, and the first node N1 is switched to the potential −3V in the (n+1)-th frame from 1.5V, in the initialization stage. And although there is a parasitic capacitance between the first node N1 and the second node N2 in the pixel circuit, the potentials of the second node n2 are reset to −0.58V and −0.59V by the reference signal in the initialization stage. Therefore, the change in voltage ΔV of the first node N1 will not have any influence upon the potential of the second node N2 in the n-th frame, and the potential of the second node N2 in the (n+1)-th frame in the initialization stage, and thus will not have any influence upon the potential of the first node N1 in the n-th frame, and the potential of the first node N1 in the (n+1)-th frame in the data writing stage, so that the brightness of the n-th frame will be the same as the brightness of the (n+1)-th frame.
In a particular implementation, in the electroluminescent display panel above according to the embodiment of the disclosure, the connection passage arranged between the every two adjacent pixel circuits of the each column of the plurality of pixel circuits may have the following several implementations.
A first implementation: the connection passage provides a reference signal to a fifth terminal of a node initialization module 101 of a latter pixel circuit of the every two adjacent pixel circuits, so that a second node N2 of the latter pixel circuit is initialized while initializing a first node N1 of the latter pixel circuit in the initialization stage; as illustrated in
A second implementation: the connection passage provides a reference signal to a third terminal of an anode reset module 102 of a former pixel circuit of the every two adjacent pixel circuits, so that an anode of the former pixel circuit is reset while initializing the second node N2 of the latter pixel circuit; and as illustrated in
A third implementation: as illustrated in
Therefore, in all the three implementations above, a second node N2 can be initialized while initializing a first node N1, so that not only the reset conditions of respective frames can be guaranteed to be completely consistent, but also the number of signal terminals can be reduced, and the wiring space can be saved; in addition, the problem of threshold voltage being differently grabbed due to a voltage jump is effectively avoided, the consistency between the brightness of the first frame after a switch between high and low gray scales is guaranteed, and the afterimage due to the deviation of the threshold voltage of the drive transistor is effectively prevented. Although the virtual pixel circuit arranged in the electroluminescent display panel is used for initializing a second node N2 or resetting a third node N3 in the third implementation mode, the operation processes of respective modules therein are the same, and have no fundamental difference in essence, if the virtual pixel circuit is regarded as a pixel circuit; therefore, the implementation of the connection passage arranged between every two adjacent pixel circuits will be described in details below by taking the first implementation and the second implementation as examples.
In one or more embodiments, for the first implementation, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
In one or more embodiments, in order to enable a potential of a reference signal as a potential of a third node N3 under the control of an anode reset module 102, thus to provide the reference signal to a fifth terminal of a node initialization module 101 of the next pixel circuit, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
In one or more embodiments, for the second implementation, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
In one or more embodiments, in order to enable a potential of a reference signal as a potential of a second node N2 under the control of a node initialization module 101, thus to provide the reference signal to a third terminal of an anode reset module 102 of a previous pixel circuit, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
It shall be noted that in the electroluminescent display panel, all scan signal terminals are arranged in a column direction and emit scan signals from a scan control driver in a mode of line by line scan to drive respective pixel circuits, so that by taking the electroluminescent display panel as a whole, the serial numbers of the scan signal terminals are continuously arranged in sequence; for example, as illustrated in
Moreover, in each pixel circuit illustrated in
In a particular implementation, in order to clearly explain the working process of each module of each pixel circuit,
In one or more embodiments, in order to achieve a function of a node initialization module 101 thus to initialize a first node N1 and a second node N2, in the electroluminescent display panel above according to the embodiment of the disclosure, in the pixel circuit P1 as illustrated in
In one or more embodiments, the first switch transistor T1 is configured to be controlled by a first scan signal input from the first scan signal terminal S1 to transmit a reference signal input from the reference signal terminal Vref to the first node N1; and the second switch transistor T2 is configured to be controlled by the first scan signal input from the first scan signal terminal S1 to transmit the received reference signal to the second node N2.
In one or more embodiments, both the first switch transistor T1 and the second switch transistor T2 may be P-type transistors, and when the first scan signal input from the first scan signal terminal S1 is at a low level, both the first switch transistor T1 and the second switch transistor T2 are in a conductive state (i.e. turned on). Both the first switch transistor T1 and the second switch transistor T2 may also be N-type transistors, and when the first scan signal input from the first scan signal terminal S1 is at a high level, both the first switch transistor T1 and the second switch transistor T2 are in a conductive state.
The particular structure of the node initialization module 101 has been described above only by way of an example, and in a particular implementation, the particular structure of the node initialization module 101 will not be limited to the structure above according to the embodiment of the disclosure, but can alternatively be another structure known to those skilled in the art, so the embodiment of the disclosure will not be limited thereto.
Further, in the pixel circuit P1 as illustrated in
Wherein a drain of the first sub-switch transistor T11 is electrically connected with a source of the second sub-switch transistor T12; a gate of the first sub-switch transistor T11 and a gate of the second sub-switch transistor T12 are electrically connected with the first scan signal terminal S1 respectively; and a source of the first sub-switch transistor T11 is electrically connected with the reference signal terminal Vref, and a drain of the second sub-switch transistor T12 is electrically connected with the first node N1.
In one or more embodiments, when the first switch transistor T1 is a P-type transistor, both the first sub-switch transistor T11 and the second sub-switch transistor T12 are P-type transistors, and when the first scan signal input from the first scan signal terminal S1 is at a low level, both the first sub-switch transistor T11 and the second sub-switch transistor T12 are in a conductive state; and when the first switch transistor T1 is an N-type transistor, both the first sub-switch transistor T11 and the second sub-switch transistor T12 are N-type transistors, and when the first scan signal input from the first scan signal terminal S1 is at a high level, both the first sub-switch transistor T11 and the second sub-switch transistor T12 are in a conductive state.
In a particular implementation, in order to achieve a function of an anode reset module 102 thus to reset an anode, in the electroluminescent display panel above according to the embodiment of the disclosure, in the pixel circuit P1 as illustrated in
In one or more embodiments, the third switch transistor T3 is configured to be controlled by a second scan signal input from the second scan signal terminal S2 to transmit the received reference signal to the third node N3.
In one or more embodiments, the third switch transistor T3 may be a P-type transistor, and when the second scan signal input from the second scan signal terminal S2 is at a low level, the third switch transistor T3 is in a conductive state. The third switch transistor T3 may also be an N-type transistor, and when the second scan signal input from the second scan signal terminal S2 is at a high level, the third switch transistor T3 is in a conductive state.
The particular structure of the anode reset module 102 has been described above only by way of an example, and in a particular implementation, the particular structure of the anode reset module 102 will not be limited to the structure above according to the embodiment of the disclosure, but can alternatively be another structure known to those skilled in the art, so the embodiment of the disclosure will not be limited thereto.
In a particular implementation, in order to achieve a function of a data writing module 103, in the electroluminescent display panel above according to the embodiment of the disclosure, in the pixel circuit P1 as illustrated in
Wherein the fourth switch transistor T4 includes a gate electrically connected with the second scan signal terminal S2, a source electrically connected with a data signal terminal Vdata, and a drain electrically connected with the second node N2; and the fifth switch transistor T5 includes a gate electrically connected with the second scan signal terminal S2, a source electrically connected with a fourth node N4, and a drain electrically connected with the first node N1.
In one or more embodiments, the fourth switch transistor T4 is configured to be controlled by a second scan signal input from the second scan signal terminal S2 to transmit a data signal input from the data signal terminal Vdata to the second node N2; and the fifth switch transistor T5 is configured to be controlled by the second scan signal input from the second scan signal terminal S2 to provide an electric potential at the fourth node N4 to the first node N1.
In one or more embodiments, both the fourth switch transistor T4 and the fifth switch transistor T5 may be P-type transistors, and when the second scan signal input from the second scan signal terminal S2 is at a low level, both the fourth switch transistor T4 and the fifth switch transistor T5 are in a conductive state. Both the fourth switch transistor T4 and the fifth switch transistor T5 may also be N-type transistors, and when the second scan signal input from the second scan signal terminal S2 is at a high level, both the fourth switch transistor T4 and the fifth switch transistor T5 are in a conductive state.
The particular structure of the data writing module 103 has been described above only by way of an example, and in a particular implementation, the particular structure of the data writing module 103 will not be limited to the structure above according to the embodiment of the disclosure, but can alternatively be another structure known to those skilled in the art, so the embodiment of the disclosure will not be limited thereto.
Similarly, in the pixel circuit P1 as illustrated in
Wherein a source of the third sub-switch transistor T51 is electrically connected with a drain of the fourth sub-switch transistor T52; a gate of the third sub-switch transistor T51 and a gate of the fourth sub-switch transistor T52 are electrically connected with the second scan signal terminal S2 respectively; and a drain of the third sub-switch transistor T51 is electrically connected with the first node N1, and a source of the fourth sub-switch transistor T52 is electrically connected with the fourth node N4.
In one or more embodiments, when the fifth switch transistor T5 is a P-type transistor, both the third sub-switch transistor T51 and the fourth sub-switch transistor T52 are P-type transistors, and when the second scan signal input from the second scan signal terminal S2 is at a low level, both the third sub-switch transistor T51 and the fourth sub-switch transistor T52 are in a conductive state. When the fifth switch transistor T5 is an N-type transistor, both the third sub-switch transistor T51 and the fourth sub-switch transistor T52 are N-type transistors, and when the second scan signal input from the second scan signal terminal S2 is at a high level, both the third sub-switch transistor T51 and the fourth sub-switch transistor T52 are in a conductive state.
In a particular implementation, in order to achieve a function of a light emitting control module 104 thus to enable a light emitting diode 106 to emit light, in the electroluminescent display panel above according to the embodiment of the disclosure, in the pixel circuit P1 as illustrated in
Wherein the sixth switch transistor T6 includes a gate electrically connected with a light emitting control signal terminal EMIT1, a source electrically connected with a first voltage signal terminal PVDD, and a drain electrically connected with the second node N2; and the seventh switch transistor T7 includes a gate electrically connected with the light emitting control signal terminal EMIT1, a source electrically connected with the fourth node N4, and a drain electrically connected with the third node N3.
In one or more embodiments, the sixth switch transistor T6 is configured to be controlled by a light emitting control signal input from the light emitting control signal terminal EMIT1 to transmit a first voltage signal input from the first voltage signal terminal PVDD to the second node N2; and the seventh switch transistor T7 is configured to be controlled by the light emitting control signal input from the light emitting control signal terminal EMIT1 to transmit the electric potential at the fourth node N4 to the third node N3.
In one or more embodiments, both the sixth switch transistor T6 and the seventh switch transistor T7 may be P-type transistors, and when the light emitting control signal input from the light emitting control signal terminal EMIT1 is at a low level, both the sixth switch transistor T6 and the seventh switch transistor T7 are in a conductive state. Both the sixth switch transistor T6 and the seventh switch transistor T7 may also be N-type transistors, and when the light emitting control signal input from the light emitting control signal terminal EMIT1 is at a high level, both the sixth switch transistor T6 and the seventh switch transistor T7 are in a conductive state.
The particular structure of the light emitting control module 104 has been described above only by way of an example, and in a particular implementation, the particular structure of the light emitting control module 104 will not be limited to the structure above according to the embodiment of the disclosure, but can alternatively be another structure known to those skilled in the art, so the embodiment of the disclosure will not be limited thereto.
In a particular implementation, in order to achieve a function of a drive control module 105 thus to drive a light emitting diode 106 to emit light, in the electroluminescent display panel above according to the embodiment of the disclosure, in the pixel circuit P1 as illustrated in
Wherein the drive transistor Md includes a gate electrically connected with the first node N1, a source electrically connected with the second node N2, and a drain electrically connected with the fourth node N4; and the capacitor C is connected between the first node N1 and the first voltage signal terminal PVDD.
In a particular implementation, the drive transistor Md and each switch transistor mentioned in the electroluminescent display panel above according to the embodiment of the disclosure can be embodied as N-type transistors, alternatively, as illustrated in
It shall be noted that in the electroluminescent display panel above according to the embodiment of the disclosure, the drive transistor Md and each switch transistor above may be thin film transistors (TFTs), or may be metal oxide semiconductors (MOSs), which will not be limited herein. In a particular implementation, a source and a drain of each transistor may be exchanged, which will not be particularly distinguished. The described particular embodiments are described by taking the drive transistor and each transistor which are thin film transistors as examples.
In a particular implementation, in the electroluminescent display panel above according to the embodiment of the disclosure, in order to prevent a certain pixel circuit of a column of pixel circuits connected from breaking down and then affecting the normal operation of other pixel circuits, in addition to the structure of a pixel circuit illustrated in
In one or more embodiments, in the pixel circuit illustrated in
Of course, the source of the second switch transistor T2 is not limited to be electrically connected with the first node N1 as illustrated in
The operation process of the pixel circuit of the electroluminescent display panel above according to the embodiment of the present disclosure will be described in details below in combination with several particular embodiments.
In one or more embodiments, the operation process of the pixel circuit of the electroluminescent display panel above according to the embodiment of the present disclosure is described below in combination with the input-output time sequence diagrams illustrated in
In one or more embodiments, the structure of the pixel circuit illustrated in
In the T1 stage, S1=0, S2=1, S3=1, EMIT1=1, EMIT2=0, and this stage is an initialization stage of the pixel circuit P1.
Since S1=0, in the pixel circuit PN−1, the first switch transistor T1 and the second switch transistor T2 are turned on, the first switch transistor T1 transmits the reference signal input from the reference signal terminal Vref to the first node N1, and the second switch transistor T2 transmits the reference signal input from the reference signal terminal Vref to the second node N2, so that N1=Vref and N2=Vref. Thus, the drive transistor Md is initialized, and the organic light emitting diode D does not emit light.
In the T2 stage, S1=1, S2=0, S3=1, EMIT1=1, EMIT2=1, and this stage is a data writing stage of the pixel circuit P1 and an initialization stage of the pixel circuit P2.
In the pixel circuit P1, since S2=0, the third switch transistor T3 is turned on and transmits the reference signal input from the reference signal terminal Vref to the third node N3, so that N3=Vref, and the anode is reset. Meanwhile, both the fourth switch transistor T4 and the fifth switch transistor T5 are in a conductive state, and the fourth switch transistor T4 transmits the data signal input from the data signal terminal Vdata to the second node N2, so that N2=Vdata; and the fifth switch transistor T5 is turned on to connect the gate of the drive transistor Md with the drain thereof, and the potentials of the first node N1 and the fourth node N4 are changed to Vdata−|Vth|. At this moment, the Vsg of the drive transistor Md is changed from 0 to Vdata−Vref to |Vth|, so the same threshold voltage can be grabbed no matter whether there is a jump from a high or low grayscale to a middle grayscale; since EMIT=1, both the sixth switch transistor T6 and the seventh switch transistor T7 are turned off, and the organic light emitting diode D does not emit light.
In the pixel circuit P2, since S2=0, the first switch transistor T1 and the second switch transistor T2 are turned on, and the first switch transistor T1 transmits the reference signal input from the reference signal terminal Vref to the first node N1, so that N1=Vref; and since the source of the second switch transistor T2 is electrically connected with the third node N3 of the pixel circuit P1, and the potential of the third node N3 of the pixel circuit P1 is Vref in this stage, the second switch transistor T2 transmits the potential Vref of the third node N3 of the pixel circuit P1 to the second node N2, so that N2=Vref, and the drive transistor Md is initialized, and the organic light emitting diode D does not emit light.
In the T3 stage, S1=1, S2=1, S3=0, EMIT1=0, EMIT2=1, and this stage is a light emitting stage of the pixel circuit P1 and a data writing stage of the pixel circuit P2.
In the pixel circuit P1, since S1=1, both the first switch transistor T1 and the second switch transistor T2 are turned off. Since S2=1, the third switch transistor T3, the fourth switch transistor T4 and the fifth switch transistor T5 are all turned off. Since EMIT1=0, the sixth switch transistor T6 is turned on to provide the high potential of the first voltage signal terminal PVDD to the source of the drive transistor Md, and the potential of the second node N2 is changed to PVDD. At this moment, in the drive transistor Md, Vsg=N2−N1=PVDD−Vdata+|Vth|, I=K(Vsg−|Vth|)2=K(PVDD−Vdata)2; and the seventh switch transistor T7 is turned on, so that the organic light emitting diode D is driven by the drive current of the drive transistor Md to emit light.
In the pixel circuit P2, since only S3=0, this stage is the data writing stage of the pixel circuit P2. Thus, the data writing stage of the pixel circuit P2 is the same as that of the pixel circuit P1, and reference can be made to the data writing stage (i.e. the T2 stage) of the pixel circuit P1 for details; so a repeated description thereof will be omitted here.
In the T4 stage, S1=1, S2=1, S3=1, EMIT1=1, EMIT2=0, and this stage is a light emitting stage of the pixel circuit P2.
In the pixel circuit P2, since EMIT2=0, this stage is the light emitting stage of the pixel circuit P2. Thus, the light emitting stage of the pixel circuit P2 is the same as that of the pixel circuit P1, and reference can be made to the light emitting stage (i.e. the T3 stage) of the pixel circuit P1 for details; so a repeated description thereof will be omitted here.
As can be known from the operation process above, a reference signal may be provided for the source of the second switch transistor T2 of the pixel circuit P2 while resetting the third node N3 (i.e. the anode) of the pixel circuit P1 by arranging a connection passage between the pixel circuit P1 and the pixel circuit P2, and thus the second node N2 of the pixel circuit P2 is initialized. Therefore, the number of signal terminals and the wiring space are effectively reduced, and the problem of threshold voltage being differently grabbed due to a voltage jump is effectively solved, thereby guaranteeing the consistency of the brightness of the first frame after switching between high and low gray scales.
In one or more embodiments, the structure of the pixel circuit illustrated in
In the T1 stage, SN−1=0, SN=1, SN+1=1, EMITN−1=1 and EMITN=0, and this stage is an initialization stage of the pixel circuit PN−1.
Since SN−1=0, in the pixel circuit PN−1, the first switch transistor T1 and the second switch transistor T2 are turned on. Thus, the first switch transistor T1 transmits the reference signal input from the reference signal terminal Vref to the first node N1, and the second switch transistor T2 transmits the reference signal input from the reference signal terminal Vref to the second node N2, so that N1=Vref and N2=Vref. The drive transistor Md is initialized, and the organic light emitting diode D does not emit light.
In the T2 stage, SN−1=1, SN=0, SN+1=1, EMITN−1=1 and EMITN=1, and this stage is a data writing stage of the pixel circuit PN−1 and an initialization stage of the pixel circuit PN.
In the pixel circuit PN, since only SN=0, this stage is the initialization stage of the pixel circuit PN, namely, the drive transistor Md is initialized so that N1=N2=Vref. Thus, the initialization stage of the pixel circuit PN is the same as that of the pixel circuit PN−1, and reference can be made to the initialization stage (i.e. the T1 stage) of the pixel circuit PN−1 for details, so a repeated description thereof will be omitted here.
In the pixel circuit PN−1, since SN=0, the third switch transistor T3 is turned on. Since the source of the third switch transistor T3 is electrically connected with the second node N2 of the pixel circuit PN, and the potential of the second node N2 of the pixel circuit PN in this stage is Vref, the third switch transistor T3 transmits the potential Vref of the second node N2 of the pixel circuit PN to the third node N3, so that N3=Vref, and the third node N3 (i.e. the anode) is reset. Meanwhile, both the fourth switch transistor T4 and the fifth switch transistor T5 are also in a conductive state, and the fourth switch transistor T4 transmits the data signal input from the data signal terminal Vdata to the second node N2, so that N2=Vdata; and the fifth switch transistor T5 is turned on to connect the gate of the drive transistor Md and the drain thereof, and the potentials of the first node N1 and the fourth node N4 are changed to Vdata−|Vth|. At this moment, Vsg of the drive transistor Md is changed from 0 to Vdata−Vref to |Vth|. Therefore, the same threshold voltage can be grabbed no matter whether there is a jump from a high or low grayscale to a middle grayscale. Since EMITN−1=1, both the sixth switch transistor T6 and the seventh switch transistor T7 are turned off, and the organic light emitting diode D does not emit light.
In the T3 stage, SN−1=1, SN=1, SN+1=0, EMITN−1=0 and EMITN=1, and this stage is a light emitting stage of the pixel circuit PN−1 and a data writing stage of the pixel circuit PN.
In the pixel circuit PN−1, since SN−1=1, both the first switch transistor T1 and the second switch transistor T2 are turned off. Since SN=1, the third switch transistor T3, the fourth switch transistor T4 and the fifth switch transistor T5 are all turned off. Since EMITN−1=0, the sixth switch transistor T6 is turned on to provide the high potential of the first voltage signal terminal PVDD to the source of the drive transistor Md, and the potential of the second node N2 is changed to PVDD. At this moment, in the drive transistor Md, Vsg=N2−N1=PVDD−Vdata+|Vth|, I=K(Vsg−|Vth|)2=K(PVDD−Vdata)2. The seventh switch transistor T7 is turned on, so that the organic light emitting diode D is driven by the drive current of the drive transistor Md to emit light.
In the pixel circuit PN, since only SN+1=0, this stage is the data writing stage of the pixel circuit PN. Thus, the data writing stage of the pixel circuit PN is the same as that of the pixel circuit PN−1, and reference can be made to the data writing stage (i.e. the T2 stage) of the pixel circuit PN−1 for details, so a repeated description thereof will be omitted here.
In the T4 stage, SN−1=1, SN=1, SN+1=1, EMITN−1=1 and EMITN=0, and this stage is a light emitting stage of the pixel circuit PN.
In the pixel circuit PN, since EMITN=0, this stage is the light emitting stage of the pixel circuit PN. Thus, the light emitting stage of the pixel circuit PN is the same as that of the pixel circuit PN−1, and reference can be made to the light emitting stage (i.e. the T3 stage) of the pixel circuit PN−1 for details, so a repeated description thereof will be omitted here.
As can be known from the operation process above, a reference signal may be provided for the source of the third switch transistor T3 of the pixel circuit PN−1 while initializing the second node N2 of the pixel circuit PN by arranging a connection passage between the pixel circuit PN−1 and the pixel circuit PN, and thus the third node N3 (i.e. the anode) of the pixel circuit PN−1 is reset. Therefore, the number of signal terminals and wiring space are effectively reduced, and the problem of threshold voltage being differently grabbed due to a voltage jump is effectively solved, thereby guaranteeing the consistency of the brightness of the first frame after switching between high and low gray scales.
In a particular implementation, in order to achieve the above drive process, in the electroluminescent display panel above according to the embodiment of the disclosure, the layout diagram of each pixel circuit is as illustrated in
In one or more embodiments, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
Further, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
In a particular implementation, in the electroluminescent display panel above according to the embodiment of the disclosure, as illustrated in
In one or more embodiments, since the layout diagram illustrated in
Based on the same inventive concept, an embodiment of the disclosure further provides a method for driving the electroluminescent display panel above according to the embodiment of the disclosure, including following operations.
Providing, by a connection passage arranged between every two adjacent pixel circuits of each column of the plurality of pixel circuits, a node initialization module of one of the every two adjacent pixel circuits with a reference signal, in an initialization stage of the one of the every two adjacent pixel circuits; or, providing, by the connection passage, an anode reset module of the one of the every two adjacent pixel circuits with a reference signal, in a data writing stage of the one of the every two adjacent pixel circuits.
In a particular implementation, in the method above according to the embodiment of the disclosure, in T1-T3 stages as illustrated in
In an initialization stage (i.e. the T1 stage), providing a first level signal to a first scan signal terminal of each pixel circuit, providing a second level signal to a second scan signal terminal and a light emitting control signal terminal of the each pixel circuit.
In a data writing stage (i.e. the T2 stage), providing the second level signal to the first scan signal terminal of the each pixel circuit, providing the first level signal to the second scan signal terminal of the each pixel circuit, and providing the second level signal to the light emitting control signal terminal of the each pixel circuit.
In a light emitting stage (i.e. the T3 stage), providing the second level signal to the first scan signal terminal of the each pixel circuit, providing the second level signal to the second scan signal terminal of the each pixel circuit, and providing the first level signal to the light emitting control signal terminal of the each pixel circuit.
In one or more embodiments, in the method for driving the electroluminescent display panel above according to the embodiment of the disclosure, the first level signal may be a high potential signal, and accordingly, the second level signal may be a low potential signal; or vice versa, as illustrated in
On the basis of the same inventive concept, an embodiment of the disclosure further provides a display device, which may include the electroluminescent display panel above according to the embodiment of the disclosure. Of course, the display device can be any product or component having a display function, such as a mobile phone (as illustrated in
Embodiments of the present disclosure provide an electroluminescent display panel and a method for driving the same, and a display device. The electroluminescent display panel includes a plurality of pixel circuits arranged in an array, each pixel circuit including a node initialization module and an anode reset module; wherein by arranging a connection passage between every two adjacent pixel circuits of each column of the plurality of pixel circuits, a reference signal is provided for either an anode reset module or a node initialization module of one of the every two adjacent pixel circuits, so that not only key nodes can be initialized via a node initialization module, thereby avoiding the problem of threshold voltage being differently grabbed due to a voltage jump and effectively preventing the afterimage from occurring as a result of the deviating threshold voltage of the drive transistor, but also the reference signal can be provided for an anode reset module or a node initialization module of an adjacent pixel circuit, thereby reducing the number of signal ports and saving wiring space.
Evidently those skilled in the art can make various modifications and variations to the disclosure without departing from the spirit and scope of the disclosure. Thus the disclosure is also intended to encompass these modifications and variations thereto so long as the modifications and variations come into the scope of the claims appended to the disclosure and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017 1 0642948 | Jul 2017 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20150379930 | Lee | Dec 2015 | A1 |
| 20170076646 | Gu et al. | Mar 2017 | A1 |
| 20170270860 | Wang | Sep 2017 | A1 |
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| 1577458 | Feb 2005 | CN |
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| 105679249 | Jun 2016 | CN |
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| Number | Date | Country | |
|---|---|---|---|
| 20180130420 A1 | May 2018 | US |
