ELECTROMAGNETIC INTERFERENCE (EMI) REDUCTION IN INTERLEAVED POWER CONVERTER

Abstract

A power converter system includes an interleaved power converter having a plurality of parallel-connected phase legs between DC terminals and an AC terminal. A plurality of parallel-connected inductors are each connected to one of the plurality of parallel-connected phase legs to provide a summed output of the parallel-connected phase legs to the AC terminal. A controller generates PWM signals used to control the state of each of the plurality of phase legs by comparing a carrier signal to a reference signal, wherein a period of the carrier signal is randomly varied from a nominal period.

Description

BACKGROUND

The present invention relates to electromagnetic interference (EMI) noise mitigation for interleaved power converters.

Switching power converters are often used to convert an alternating current (AC) voltage into a direct current (DC) voltage, or to convert a DC voltage into an AC voltage. One example of such a power converter is a two-level (2L) converter, which is able to synthesize two node voltages (“levels”) at a phase terminal. These converters typically use pulse-width modulation (PWM) at a fixed switching frequency in order to approximate a desired continuous waveform. PWM is known to cause distortions in the output waveform, which are typically undesirable.

SUMMARY

A power converter system is disclosed herein that includes an interleaved power converter having a plurality of parallel-connected phase legs between DC terminals and an AC terminal. A plurality of parallel-connected inductors are each connected to one of the plurality of parallel-connected phase legs to provide a summed output of the parallel-connected phase legs to the AC terminal. A controller generates PWM signals used to control the state of each of the plurality of phase legs by comparing a carrier signal to a reference signal, wherein a period of the carrier signal is randomly varied from a nominal period.

A controller is disclosed herein for providing PWM control of an interleaved power converter having at least a first phase leg and a second phase leg. The controller includes a random value generator that randomly generates values within a pre-determined range, a summer that adds the values generated by the random number generator to a nominal value to define a period of a carrier signal, a carrier signal generator that generates a first carrier signal having a period defined by the output of the summer, wherein the period of the carrier signal is varied from a nominal period by the addition of the random value provided by the random value generator to the nominal value, a phase adjuster that generates a second carrier signal shifted in phase related to the first carrier signal, a first comparator that compares the first carrier signal to a reference signal to generate first PWM signals used to control a state of the first phase leg of the interleaved power converter, and a second comparator that compares the second carrier signal to the reference signal to generate second PWM signals used to control a state of the second phase leg of the interleaved power converter.

A method of reducing EMI of an interleaved power converter is disclosed herein. The method includes generating random values, periodically adjusting a nominal value with a generated random value to determine a randomized period of a first carrier signal, generating the first carrier signal having the randomized period, generating a second carrier signal that is phase shifted relative to the first carrier signal, generating first PWM signals used to control a state of a first phase leg of the interleaved power converter by comparing the first carrier signal to a reference signal, generating second PWM signals used to control a state of a second phase leg of the interleaved power converter by comparing the second carrier signal to the reference signal, and providing the first and second PWM signals to the interleaved power converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of an interleaved power converter system.

FIG. 2 is a functional block diagram illustrating functions performed by a controller in generating pulse width modulation (PWM) control signals provided to the interleaved power converter system.

FIG. 3 is a waveform diagram illustrating carrier signals generated according to an embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating carrier signals generated according to another embodiment of the present invention.

FIG. 5 is a waveform diagram illustrating carrier signals generated according to a further embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a schematic diagram of an embodiment of an interleaved power converter system 10, which includes two-level (2L) converter 12 and controller 14. Two-level converter 12 includes interleaved phase legs 16a, 16b and 16c and interleaving magnetics 18 connected between DC terminals DC+ and DC− and AC terminal AC˜. Phase leg 16a includes transistors Q1 and Q2 and diodes D1 and D2, phase leg 16b includes transistors Q3 and Q4 and diodes D3 and D4, and phase leg 16c includes transistors Q5 and Q6 and diodes D5 and D6. Interleaving magnetics 18 include inductors L1, L2 and L3 connected to respective phase legs 16a, 16b and 16c.

Each of phase legs 16a, 16b and 16c is able to synthesize two node voltages (“levels”) at respective phase for connection to AC terminal AC˜. For example, referring to phase leg 16a, transistor Q1 is turned on (with transistor Q2 turned off) to synthesize an output node voltage equal to the DC+ node voltage, and transistor Q2 is turned on (with transistor Q1 turned off) in order to synthesize an output node voltage equal to the DC− node voltage. Phase leg 16a is able to use pulse-width modulation (PWM) at a fixed switching frequency to control the switching of transistors Q1 and Q2 in order to approximate a desired continuous waveform. The same is true for phase legs 16b and 16c, with each of the phase legs being offset from one another by a phase delay. The pulse-width modulated switching signals are shown as signals S_Q1, S_Q2, S_Q3, S_Q4, S_Q5 and S_Q6 output from controller 14 to two-level converter 12.

PWM-created waveforms are subject to distortion—that is, a true continuous waveform is typically not achieved. The distortion of the output waveform from a true continuous waveform creates electromagnetic interference (EMI). Interleaving provides the advantage of reducing EMI at the output of the combined parallel phase legs 16a, 16b and 16c. In addition, the peak amplitudes of the EMI/distortions of the output waveform in the frequency domain may be further reduced by adding random fractional variation to the PWM switching frequency. An interleaved power converter system controller that employs random fractional variation of a carrier signal in order to minimize EMI in the output waveform is shown in FIG. 2.

FIG. 2 is a functional block diagram illustrating functions performed by controller 14 in generating PWM control signals S_Q1, S_Q2, S_Q3, S_Q4, S_Q5 and S_Q6 provided to the interleaved power converter system 10 (FIG. 1). A carrier wave having period t_p is generated by summing nominal carrier period 20 and an output of random number generator 22 (which generates appropriately range-limited random values that may be positive or negative in an exemplary embodiment). Carrier wave generator 24 generates carrier wave CW1 having period t_p. In addition, carrier wave CW2 is generated by applying phase delay 26 (a delay of t_p/3 in the depicted embodiment) to the output of carrier wave generator 24, and carrier wave CW3 is generated by applying phase delay 28 (a delay of 2t_p/3 in the depicted embodiment) to the output of carrier wave generator 24. Phase delay between each successive carrier wave is t_p/n_c, wherein n_c is the number of interleaved phase legs. Low frequency reference signal 30, such as a sinusoidal voltage reference signal in an exemplary embodiment, is compared to high frequency carrier signals CW1, CW2 and CW3, which may be triangular wave signals in an exemplary embodiment, by comparators 32a, 32b and 32c. The output of comparator 32a, delayed by turn-on delay 35a, provides switching control signal S_Q1, and the output of comparator 32a, inverted by inverter 34a and delayed by turn-on delay 35b, provides switching control signal S_Q2. Similarly, the output of comparator 32b, delayed by turn-on delay 35c, provides switching control signal S_Q3, and the output of comparator 32b, inverted by inverter 34b and delayed by turn-on delay 35d, provides switching control signal S_Q4 Likewise, output of comparator 32c, delayed by turn-on delay 35e, provides switching control signal S_Q5, and the output of comparator 32c, inverted by inverter 34c and delayed by turn-on delay 35f, provides switching control signal S_Q6. Switching control signals S_Q1, S_Q2, S_Q3, S_Q4, S_Q5 and S_Q6 are used to turn on and off transistors Q1, Q2, Q3, Q4, Q5 and Q6 (FIG. 1), respectively.

By applying phase shifts between high frequency carrier signals CW1, CW2 and CW3 used for each phase leg 16a, 16b and 16c (FIG. 1), certain frequencies of EMI can be eliminated or significantly reduced. Additional EMI can occur in high frequency components of the AC node voltage (at terminal AC˜, FIG. 1) at a multitude of discrete frequencies in the infinite frequency set of n(1/t_c)+/−m(1/t_r), where n and m are integers, t_c is the nominal carrier period and t_r is the reference signal period. This EMI is mitigated by the utilization of random number generator 22. Specifically, random number generator 22 is used to make an adjustment to nominal carrier period 20 (t_c), such as by adding a positive or negative random value, which results in the high frequency EMI components of the output waveform being spread (or smeared) from the discrete frequencies at which high peak magnitudes of EMI would otherwise occur in a carrier-based PWM scheme, to a band of frequencies spread around these discrete frequencies with reduced peak magnitudes of EMI. This concept is illustrated graphically in the waveform diagrams of FIGS. 3, 4 and 5.

FIG. 3 is a waveform diagram illustrating carrier signals CW1, CW2 and CW3 generated according to an embodiment of the present invention. As shown, carrier signal CW1 has a first period in the first time interval I1, has a second period in the second time interval I2, and has a third period in the third time interval I3. These varying, randomized periods are set in an exemplary embodiment by adding/subtracting a random number (generated by random number generator 22, FIG. 2) to/from a nominal carrier signal period. A new randomized period is generated in this embodiment at each full period of carrier signal CW1, so that each of time intervals I1, I2 and I3 begins after a full carrier signal period has been completed for carrier signal CW1. Carrier signal CW2 is delayed from carrier signal CW1 by one-third of the carrier signal period, and carrier signal CW3 is delayed from carrier signal CW1 by two-thirds of the carrier signal period.

FIG. 4 is a waveform diagram illustrating carrier signals CW1, CW2 and CW3 generated according to another embodiment of the present invention. As shown, carrier signal CW1 has varying, randomized periods in each of time intervals J1, J2, J3, J4 and J5. These varying, randomized periods are set in an exemplary embodiment by adding/subtracting a random number (generated by random number generator 22, FIG. 2) to/from a nominal carrier signal period. A new randomized period is generated in this embodiment at each half period of carrier signal CW1, so that each of time intervals J1, J2, J3, J4 and J5 begins after a half carrier signal period has been completed for carrier signal CW1. Carrier signal CW2 is delayed from carrier signal CW1 by one-third of the carrier signal period, and carrier signal CW3 is delayed from carrier signal CW1 by two-thirds of the carrier signal period.

FIG. 5 is a waveform diagram illustrating carrier signals CW1, CW2 and CW3 generated according to a further embodiment of the present invention. As shown, carrier signal CW1 has varying, randomized periods in each of time intervals K1 and K2. These varying, randomized periods are set in an exemplary embodiment by adding/subtracting a random number (generated by random number generator 22, FIG. 2) to/from a nominal carrier signal period. A new randomized period is generated in this embodiment after two full periods of carrier signal CW1, so that each of time intervals K1 and K2 begins after two full carrier signal periods have been completed for carrier signal CW1. Carrier signal CW2 is delayed from carrier signal CW1 by one-third of the carrier signal period, and carrier signal CW3 is delayed from carrier signal CW1 by two-thirds of the carrier signal period.

In the embodiments shown in FIGS. 3-5, the variation of the carrier signal period results in a spreading or smearing of the high frequency EMI noise components of the AC output voltage from the discrete frequencies where these EMI noise components have high peak magnitudes, so that the high frequency EMI noise components are seen across a wide band of frequencies with reduced peak amplitudes.

While examples of the present invention have been shown in FIGS. 3-5 where a new randomized period is generated to adjust the period of the carrier signals at full, half, and two period intervals, it should be understood that other timing arrangements for the generation of a new random number to adjust the carrier signal period are possible and contemplated herein, such as other fractions or multiples of the carrier signal period, based on a timer that is unrelated to the carrier signal period, or other arrangements.

While examples of the present invention have been shown and described herein for an interleaved power converter having three phase legs, it should be understood that any number of interleaved phase legs may be employed utilizing the principles and concepts described herein.

DISCUSSION OF POSSIBLE EMBODIMENTS

The following are non-exclusive descriptions of possible embodiments of the present invention.

A power converter system includes, among other things, an interleaved power converter having a plurality of parallel-connected phase legs connected between DC terminals and an AC terminal, a plurality of parallel-connected inductors each connected to one of the plurality of parallel-connected phase legs to provide a summed output of the parallel-connected phase legs to the AC terminal, and a controller that generates PWM signals used to control the state of each of the plurality of phase legs by comparing a carrier signal to a reference signal, wherein a period of the carrier signal is randomly varied from a nominal period.

The power converter system of the preceding paragraph can optionally include, additionally and/or alternatively, any one or more of the following features, configurations and/or additional components:

The controller includes a random number generator that generates random values, within a pre-determined numeric range, that vary the period of the carrier signal from the nominal period.

The random values generated by the random number generator vary the period of the carrier signal at half-cycle intervals of the carrier signal.

The random values generated by the random number generator vary the period of the carrier signal at full-cycle intervals of the carrier signal.

The random values generated by the random number generator vary the period of the carrier signal at multiple-cycle intervals of the carrier signal.

The plurality of parallel-connected phase legs includes a first phase leg, a second phase leg, and a third phase leg.

The plurality of parallel-connected inductors includes a first inductor connected between the first phase leg and the AC terminal, a second inductor connected between the second phase leg and the AC terminal, and a third inductor connected between the third phase leg and the AC terminal.

The carrier signal is divided into a first carrier signal, a second carrier signal phase shifted relative to the first carrier signal, and a third carrier signal phase shifted relative to the first and second carrier signals.

A controller for providing pulse-width modulation control of an interleaved power converter having at least a first phase leg and a second phase leg includes, among other things, a random value generator that randomly generates values, a summer that adds the values generated by the random value generator to a nominal value to define a period of a carrier signal, a carrier signal generator that generates a first carrier signal having a period defined by the output of the summer, wherein the period of the carrier signal is varied from a nominal period by the addition of the random value provided by the random value generator to the nominal value, a phase adjustor that generates a second carrier signal shifted in phase relative to the first carrier signal, a first comparator that compares the first carrier signal to a reference signal to generate first pulse-width modulated (PWM) signals used to control a state of the first phase leg of the interleaved power converter, and a second comparator that compares the second carrier signal to the reference signal to generate second PWM signals used to control a state of the second phase leg of the interleaved power converter.

The controller of the preceding paragraph can optionally include, additionally and/or alternatively, any one or more of the following features, configurations and/or additional components:

The random value generator randomly generates positive and negative values.

The output of the random value generator is range-limited such that the random values may not exceed minimum and maximum limits.

The period of the first carrier signal is modified once per half-cycle of the first carrier signal.

The period of the first carrier signal is modified once per cycle of the first carrier signal.

The period of the first carrier signal is modified once per multiple cycles of the first carrier signal.

The first and second PWM signals each comprise two complementary PWM signals.

A method of reducing electromagnetic interference (EMI) of an interleaved power converter includes, among other things, generating random values, periodically adjusting a nominal value with a generated random value to determine a randomized period of a first carrier signal, generating the first carrier signal having the randomized period, generating a second carrier signal that is phase shifted relative to the first carrier signal, generating first pulse-width modulation (PWM) signals used to control a state of a first phase leg of the interleaved power converter by comparing the first carrier signal to a reference signal, generating second pulse-width modulation (PWM) signals used to control a state of a second phase leg of the interleaved power converter by comparing the second carrier signal to the reference signal, and providing the first and second PWM signals to the interleaved power converter.

The method of the preceding paragraph can optionally include, additionally and/or alternatively, any one or more of the following features, configurations and/or additional steps:

The random values are positive and negative values, and adjusting the nominal value with the generated random value comprises adding the generated random value to the nominal value to determine the randomized period of the first carrier signal.

The output of the random value generator is range-limited such that the random values may not exceed minimum and maximum limits.

The period of the first carrier signal is modified once per half-cycle of the first carrier signal.

The period of the first carrier signal is modified once per cycle of the first carrier signal.

The period of the first carrier signal is modified once per multiple cycles of the first carrier signal.

The first and second PWM signals each comprise two complementary PWM signals.

While the invention has been described with reference to an exemplary embodiment(s), it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment(s) disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

1. A power converter system comprising: an interleaved power converter having a plurality of parallel-connected phase legs connected between direct current (DC) terminals and an alternating current (AC) terminal;a plurality of parallel-connected inductors each connected to one of the plurality of parallel-connected phase legs to provide a summed output of the parallel-connected phase legs to the AC terminal; anda controller that generates pulse-width modulation (PWM) signals used to control the state of each of the plurality of phase legs by comparing a carrier signal to a reference signal, wherein a period of the carrier signal is randomly varied from a nominal period.

2. The power converter system of claim 1, wherein the controller includes a random number generator that generates random values that vary the period of the carrier signal from the nominal period.

3. The power converter system of claim 2, wherein the random values generated by the random number generator vary the period of the carrier signal at half-cycle intervals of the carrier signal.

4. The power converter system of claim 2, wherein the random values generated by the random number generator vary the period of the carrier signal at full-cycle intervals of the carrier signal.

5. The power converter system of claim 2, wherein the random values generated by the random number generator vary the period of the carrier signal at multiple-cycle intervals of the carrier signal.

6. The power converter system of claim 1, wherein the plurality of parallel-connected phase legs includes a first phase leg, a second phase leg, and a third phase leg.

7. The power converter system of claim 6, wherein the plurality of parallel-connected inductors includes a first inductor connected between the first phase leg and the AC terminal, a second inductor connected between the second phase leg and the AC terminal, and a third inductor connected between the third phase leg and the AC terminal.

8. The power converter system of claim 7, wherein the carrier signal is divided into a first carrier signal, a second carrier signal phase shifted relative to the first carrier signal, and a third carrier signal phase shifted relative to the first and second carrier signals.

9. A controller for providing pulse-width modulation control of an interleaved power converter having at least a first phase leg and a second phase leg, the controller comprising: a random value generator that randomly generates values;a summer that adds the values generated by the random value generator to a nominal value to define a period of a carrier signal;a carrier signal generator that generates a first carrier signal having a period defined by the output of the summer, wherein the period of the carrier signal is varied from a nominal period by the addition of the random value provided by the random value generator to the nominal value;a phase adjustor that generates a second carrier signal shifted in phase relative to the first carrier signal;a first comparator that compares the first carrier signal to a reference signal to generate first pulse-width modulated (PWM) signals used to control a state of the first phase leg of the interleaved power converter; anda second comparator that compares the second carrier signal to the reference signal to generate second PWM signals used to control a state of the second phase leg of the interleaved power converter.

10. The controller of claim 9, wherein the random value generator randomly generates positive and negative values.

11. The controller of claim 9, wherein the period of the first carrier signal is modified once per half-cycle of the first carrier signal.

12. The controller of claim 9, wherein the period of the first carrier signal is modified once per cycle of the first carrier signal.

13. The controller of claim 9, wherein the period of the first carrier signal is modified once per multiple cycles of the first carrier signal.

14. The controller of claim 9, wherein the first and second PWM signals each comprise two complementary PWM signals.

15. A method of reducing electromagnetic interference (EMI) of an interleaved power converter, the method comprising: generating random values;periodically adjusting a nominal value with a generated random value to determine a randomized period of a first carrier signal;generating the first carrier signal having the randomized period;generating a second carrier signal that is phase shifted relative to the first carrier signal;generating first pulse-width modulation (PWM) signals used to control a state of a first phase leg of the interleaved power converter by comparing the first carrier signal to a reference signal;generating second pulse-width modulation (PWM) signals used to control a state of a second phase leg of the interleaved power converter by comparing the second carrier signal to the reference signal; andproviding the first and second PWM signals to the interleaved power converter.

16. The method of claim 15, wherein the random values are positive and negative values, and adjusting the nominal value with the generated random value comprises adding the generated random value to the nominal value to determine the randomized period of the first carrier signal.

17. The method of claim 15, wherein the period of the first carrier signal is modified once per half-cycle of the first carrier signal.

18. The method of claim 15, wherein the period of the first carrier signal is modified once per cycle of the first carrier signal.

19. The method of claim 15, wherein the period of the first carrier signal is modified once per multiple cycles of the first carrier signal.

20. The method of claim 15, wherein the first and second PWM signals each comprise two complementary PWM signals.