Patent Application
20060261725
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C.§119 from an application entitled Electron Emission Device, Electron Emission Display, And Manufacturing Method Of The Electron Emission Device earlier filed in the Korean Intellectual Property Office on the 19th of May 2005 and there duly assigned Serial No. 10-2005-0041982.
1. Field of the Invention
The present invention relates to electron emission devices and to devices incorporating electron emission devices generally, and in particular, to electron emission devices having gate electrodes constructed with an enhanced structure to improve the light emission uniformity per pixel, and methods for manufacturing electron emission devices and electron emission displays using these electron emission devices.
2. Description of the Related Art
Generally, electron emission elements are classified on the basis of the type of electron source which they employ, as either a first type using a hot cathode, or a second type using a cold cathode.
Among the second type electron emission elements which use a cold cathode, are a field emission array (FEA) type, a surface conduction emission (SCE) type, a metal-insulator-metal (MIM) type, and a metal-insulator-semiconductor (MIS) type.
The FEA-type electron emission element has electron emission regions, and has a cathode electrode and a gate electrode as its driving electrodes. The electron emission regions are formed with a material having either a low work function or a high aspect ratio, such as a carbonaceous material or a nanometer-sized material. The FEA-type electron emission element is based on the principle that when such a material having a low work function or a high aspect ratio is used in the electron emission regions, application of an electric field to the electron emission regions held under a vacuum atmosphere enables the emission of electrons from the electron emission regions.
Arrays of the electron emission elements are arranged on a first substrate to form an electron emission unit, which, in turn, forms an electron emission device together with the first substrate. A light emission unit is formed with phosphor and black layers on a surface of a second substrate facing the first substrate, an anode electrode, etc. The light emission unit formed on the second substrate is assembled with the electron emission device to thereby construct an electron emission display.
With the common FEA-type electron emission display, cathode electrodes, an insulating layer, and the gate electrodes are sequentially formed on the first substrate, and openings are formed at the gate electrodes and the insulating layer in correspondence with the respective crossed regions of the cathode and the gate electrodes. Electron emission regions are formed on the cathode electrodes within the openings. Phosphor and black layers, and an anode electrode are formed on a surface of the second substrate facing the first substrate.
When predetermined driving voltages are applied to the cathode and the gate electrodes, electric fields are formed around the electron emission regions at the pixels where the voltage difference between the two electrodes exceeds a threshold value, and electrons are emitted from those electron emission regions. The emitted electrons are attracted by the high voltage of about several kilovolts (kV) applied to the anode electrode, and accelerated toward the second substrate, followed by excitation of the phosphors at the relevant pixels and displaying the desired images.
With the structure for an electron emission display discussed in the foregoing paragraphs, it is very difficult to reliably and uniformly fabricate all of the cathode electrodes, the gate electrodes, the electron emission regions, and other structural features of the emission device. Specifically, in constructing a device with a plurality of electron emission regions formed at each pixel, many difficulties are encountered in endeavors to heighten the uniformity of shape (i.e., to provide “shape uniformity”) of the respective structural components. The factors contributing to non-uniformity deleteriously effect the uniformity of light emission per pixel and the accompanying display image quality.
It is therefore, one object of the present invention to provide an improved electron emission device.
It is another object to provide an electron emission device endowed with a greater shape uniformity between its structural components.
It is still another object to provide an electron emission device able to enhance the uniformity of electron emission by each pixel.
It is yet another object to provide a method of manufacturing an electron emission device able to enhance the uniformity of electron emission by each pixel.
It is a further object to provide an electron emission display constructed with an electron emission device able to enhance the uniformity of electron emission by each pixel.
In one exemplary embodiment of the present invention, there is provided an electron emission device that heightens the electron emission uniformity per pixel, a method of manufacturing the electron emission device, and an electron emission display using the electron emission device.
According to one exemplary embodiment of the present invention, an electron emission device includes a substrate, cathode electrodes formed on the substrate in a direction of the substrate, gate electrodes crossing over the cathode electrodes while interposing an insulating layer, openings formed in the gate electrodes and the insulating layer, and electron emission regions placed on the cathode electrodes within the respective openings. Each gate electrode has a main body, isolated portions surrounding the respective electron emission regions and isolated from the main body with a distance, and a connector interconnecting at least one of the isolated portions and the main body.
The respective isolated portions may be divided into two or more sub-portions around the relevant opening, and at least one of the divided sub-portions may be connected to the main body via the connector.
The connectors may be selectively cut to control the electron emission uniformity per pixel.
The electron emission device may further include a focusing electrode placed over the gate electrodes while interposing an additional insulating layer. The focusing electrode has openings for passing the electron beams.
According to another exemplary embodiment of the present invention, an electron emission display includes first and second substrates facing each other, cathode electrodes formed on the first substrate in a direction of the first substrate, gate electrodes crossing over the cathode electrodes while interposing an insulating layer, openings formed in the gate electrodes and the insulating layer, electron emission regions placed on the cathode electrodes within the respective openings, phosphor layers formed on a surface of the second substrate, and an anode electrode formed on a surface of the phosphor layers. Each gate electrode has a main body, isolated portions surrounding the respective electron emission regions and isolated from the main body with a distance, and a connector interconnecting at least one of the isolated portions and the main body.
The respective isolated portions may be divided into two or more sub-portions around the relevant opening, and at least one of the divided sub-portions may be connected to the main body via the connector.
The connectors may be selectively cut to control the light emission uniformity of each pixel.
The electron emission display may further include a focusing electrode placed over the gate electrodes while interposing an additional insulating layer. The focusing electrode has openings for passing the electron beams.
According to another exemplary embodiment of the present invention, in a method of manufacturing an electron emission device, cathode electrodes, an insulating layer and main bodies of gate electrodes are first formed on a substrate in a sequential manner. Openings are formed at the main bodies of the gate electrodes and the insulating layer, and simultaneously, isolated portions are formed around the openings such that the isolated portions are spaced apart from the main bodies with a distance, together with connectors interconnecting the main bodies and the isolated portions. Electron emission regions are formed within the respective openings. The light emission uniformity per pixel is tested while applying voltages to the cathode and the gate electrodes. At least one connector is selectively removed from the abnormally bright pixels among the pixels largely differentiated in the light emission uniformity.
The step of forming the isolated portions and the connectors may be conducted simultaneously with the step of forming the main bodies.
The testing of the light emission uniformity per pixel may be made using a white balance tester based on a vacuum chamber.
Alternatively, the testing of the light emission uniformity per pixel maybe made using a white balance tester after the substrate bearing the cathode and another substrate with a light emission unit are assembled and sealed to each other.
The removal of the connectors may be made by a laser, and the connectors may be formed with a width of several to several tens micrometers (μm).
A more complete appreciation of the invention and many of the attendant advantages 8 thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:
As shown in FIGS. 1 to 3, an electron emission display constructed as a first embodiment according to the principles of the present invention includes first and second substrates 10 and 12 facing each other in parallel while separated by a predetermined distance, an electron emission unit 100 provided on the first substrate 10, and a light emission unit 110 provided on a surface of the second substrate 12 facing the first substrate 10.
A sealing member (not shown) is provided at the peripheries of the first and the second substrates 10 and 12 to seal them, and the internal space between the two substrates 10 and 12 is evacuated to be at 10−6 Torr, thereby constructing a vacuum vessel with the first and the second substrates 10 and 12 and the sealant.
The electron emission unit 100 includes cathode electrodes 14 placed on the first substrate 10 and spaced apart from each other by gaps 15 in parallel with a predetermined distance, gate electrodes 18 crossing successively over the cathode electrodes 14 while an insulating layer 16 is interposed between cathode electrodes 14 and gate electrodes 18, and electron emission regions 20 formed on cathode electrodes 14 within orifices 21 extending through insulating layer 16 at the crossed regions between cathode and gate electrodes 14 and 18.
When the crossed, or overlapping regions of cathode and the gate electrodes 14 and 18 are defined as pixels, a plurality of electron emission regions 20 are formed on cathode electrodes 14 at the respective pixels. Openings, or orifices 21 are formed through insulating layer 16 and gate electrodes 18 corresponding to the respective electron emission regions 20 to expose electron emission regions 20 to the underlying major surface of first substrate 10.
It is illustrated in the drawings that nine generally circular cylindrically shaped electron emission regions are formed at each pixel in the cumulative shape of square, but the plane shape, number per pixel and arrangement of the electron emission regions 20 are not limited thereto to the specific numbers or geometric constructs illustrated.
Electron emission regions 20 may be formed from a material emitting electrons when an electric field is applied thereto under a vacuum atmosphere, such as a carbonaceous material or a nanometer (nm)-sized material. For instance, electron emission regions 20 may be formed with carbon nanotube, graphite, graphite nanofiber, diamond, diamond-like carbon, fullerene C60, silicon nanowire, or a combination thereof. The formation of the electron emission regions 20 may be made by processes such as screen printing, direct growth, chemical vapor deposition, or sputtering.
Light emission unit 110 will be now explained in detail. Phosphor layers 22 with red, green and blue phosphor layers 22R, 22G and 22B are formed on a major surface of second substrate 12 facing first substrate 10 such that substrates 10, 12 are spaced apart from each other by a distance, and black layer 24 is formed between respective phosphor layers 22 to enhance the screen contrast. Phosphor layers 22 are arranged in a distributed array to that one of the three-colored phosphor layers 22R, 22G and 22B is correspondingly located to extend across each pixel.
Anode electrode 26 is formed on the phosphor and the black layers 22 and 24 with a metallic material such as aluminum Al. Anode electrode 26 receives a high voltage required for accelerating electron beams from the outside to place phosphor layers 22 in a high potential state, and reflects the visible rays radiated from phosphor layers 22 to first substrate 10, toward second substrate 12 in order to heighten the screen luminance.
Meanwhile, anode electrode 26 may be formed with a transparent conductive material such as indium tin oxide (ITO). In this case, anode electrode is placed on a surface of the phosphor and the black layers 22 and 24 and is directed toward second substrate 12. It is also possible that a metallic layer and a transparent conductive layer be simultaneously formed to function as anode electrode 26.
As shown in
In this embodiment, gate electrode 18 is formed with a main body 30, and isolated portions 32 that are isolated from main body 30 by a distance and surround the corresponding electron emission regions 20; connectors 34 electrically interconnecting main body 30 and isolated portions 32.
Isolated portion 32 is formed in the shape of a ring that coaxially corresponds to the shape of the opening 21. Connector 34 may be provided to the corresponding isolated portion 32 placed within each pixel. Alternatively, connector 34 may be omitted at one or more isolated portions 32 within the pixel.
After the identification of the light emission uniformity per pixel such as a white balance, it is possible to selectively cut and remove one or more of connectors 34 in order to control the electron emission uniformity at each pixel.
For instance, as shown in
Consequently, it is possible to control the amount of electron emission and the luminance of each pixel by removing one or more connectors 34 from the those pixels that are overly bright (that is, from those pixels with a high luminance) in comparison to other pixels.
The difference in the light emission uniformity per pixel is usually made due to one or more of such factors as the local non-uniformity in the dimension of the electrical currents applied to cathode and gate electrodes 14, 18, the shape non-uniformity of electron emission regions 20, and the non-uniformity in the amount of electron emission.
With the inventive structure, it is possible to control the intensity in the electric field around electron emission regions 20 by selectively isolating isolated portions 32 of gate electrode 18 from main body 30 thereof, and to thereby enhance the whole light emission uniformity per pixel.
In this case, it is possible to control the light emission uniformity per pixel more precisely, compared to the previously-described structure where one isolated portion 32 is provided at each electron emission region 20.
As shown in
Focusing electrode 40 focuses the electrons emitted from electron emission regions 20, and prevents electron emission regions 20 from being influenced by the anode electric field.
The formation of cathode electrodes 14, insulating layer 16, main bodies 30 of gate electrodes 18 and electron emission regions 20 may be made using the common processing steps in various ways, and any further explanation beyond the foregoing detailed explanation will be omitted.
Process P30 for forming main bodies 30 of gate electrodes 18, and process P40 for forming isolated portions 32 and connectors 34 may be simultaneously conducted through photolithography. At this time, the process of forming openings 21 at the main bodies of gate electrodes 18 and insulating layer 16 maybe also conducted.
Process P60 of testing the white balance and identifying the light emission uniformity per pixel may be conducted using white balance tester 42 based on a vacuum chamber after electron emission unit 100 is formed on first substrate 10. Alternatively, such a process may be conducted using a while balance tester not based on the vacuum chamber after the first substrate with electron emission unit 100 and second substrate 12 with for the light emission unit are assembled and sealed to each other.
In case the white balance testing is made after only electron emission unit 100 is formed on first substrate 10, the pixels largely differentiated in the light emission uniformity per pixel are precisely checked, and specific connectors 34 are removed from the checked pixels during subsequent process P70 by using the direct precise laser processing.
By contrast, in case the white balance testing is conducted after the first and the second substrates are assembled and sealed to each other, the pixels largely differentiated in the light emission uniformity per pixel are precisely checked, and specific connectors 34 are removed from the checked pixels during subsequent process P70 using the laser processing. In order to prevent the anode electrode from being damaged due to the laser processing, a material 8 reactant with a specific wavelength of laser may be coated on connectors 34 during formation process P40.
When width of the connector 34 is in the range of between several micrometers (μm) to several micrometers (μm), the display image quality is not reduced even though the anode electrode may have become damaged due to the laser processing.
Although preferred embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concept herein taught which may appear to those skilled in the art will still fall within the spirit and scope of the present invention, as defined in the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2005-041982 | May 2005 | KR | national |
