In exemplary embodiments of the present invention, “light emission device” refers to all devices that emit visible light. Accordingly, all displays that display symbols, letters, numbers, and images to transmit information are also encompassed within the meaning of the term light emission device as it is used herein. In addition, light emission device may also refer to light sources that provide light to a non-emissive display panel.
Referring to
An electron emission device 100 formed by an array of electron emission elements is provided on a surface of the first substrate 10 facing the second substrate 12. The first substrate 10 having the electron emission device 100 and the second substrate 12 having a light emission unit 200 are combined to form the light emission device.
Cathode electrodes 14 are formed on the first substrate 10 in a stripe pattern and along a first direction (y-direction shown in
In this embodiment, each of the cathode electrodes 14 includes a resistive layer 20 having formed therein a plurality of first openings 201 at each region of crossed between the cathode electrodes 14 and the gate electrodes 18, and a conductive layer 22 formed on the resistive layer 20 and having formed therein a plurality of second openings 221 positioned corresponding to the first openings 201 to thereby spatially communicate with the first openings 201.
The second openings 221 have a larger diameter than a diameter of the first openings 201 so as to surround the first openings 201 and in a manner each exposing a predetermined area of the resistive layer 20. Stated differently, circumferential wall portions of the conductive layer 22 defining the second openings 221 maintain a predetermined distance respectively from circumferential wall portions of the resistive layer 20 defining the first openings 201.
Third and fourth openings 181, 161 are formed respectively in the gate electrodes 18 and the insulation layer 16. Each pair of one of the third openings 181 and one of the fourth openings 161 spatially communicates with a respective one of the pairs of one of first openings 201 and one of the second openings 221. Electron emission regions 24 are disposed on the first substrate 10 respectively filling the first openings 201 in the resistive layers 20, such that the electron emission regions 24 are exposed to the second substrate 12.
The second openings 221 in the conductive layer 22 are larger in size than first openings 201 in the resistive layers 20 by a predetermined ratio. One of the second openings 221 and one of the first openings 201 forming each pair of the same have aligned central axes. Accordingly, a predetermined spacing is present between the conductive layer 22 and a circumference of each of the electron emission regions 24.
At each of the crossed regions between the cathode electrodes 14 and the gate electrodes 18, one or more rows of the pairs of the first and second openings 201, 221 are formed along the first direction in the resistive layer 20 and the conductive layer 22, respectively. In
The resistive layers 20 may be formed by amorphous silicon doped with p- or n-type impurities, and may have a specific resistance of approximately 10,000 to 100,000 Ωcm. The conductive layers 22 are formed by a material having a lower specific resistance than that of the resistive layers 20, for example, a metal material such as chrome, molybdenum, aluminum, or titanium.
The electron emission regions 24 are formed of a material emitting electrons when an electric field is applied thereto under a vacuum atmosphere, such as a carbon-based material or a nanometer-sized material. For example, the electron emission regions 24 may include any one selected from the group consisting of carbon nanotubes, graphite, graphite nanofibers, diamonds, diamond-like carbon, fullerene (C60), silicon nanowires, and any combination thereof. Further, screen-printing, direct growth, chemical vapor deposition (CVD), or sputtering may be used to manufacture the electron emission regions 24.
Phosphor layers 26 (e.g., red, green, and blue phosphor layers 26R, 26G, 26B) are formed on a surface of the second substrate 12 facing the first substrate 10 and in such a manner that a predetermined spacing is provided between adjacent pairs of the phosphor layers 26. A black layer 28 is formed between adjacent pairs of the phosphor layers 26 to enhance screen contrast. The phosphor layers 26 are disposed in such a manner that one of the phosphor layers 26 of a single color corresponds in location to each crossed region of the cathode and gate electrodes 14, 18.
An anode electrode 30 is formed on the phosphor layers 26 and the black layers 28, and is formed by a metal material such as aluminum (Al). The anode electrode 30 is an acceleration electrode that receives a high voltage to maintain the phosphor layers 26 at a high electric potential state, and also functions to enhance luminance by reflecting visible light. That is, among the visible light emitted from the phosphor layers 26, the visible light that is emitted from the phosphor layers 26 toward the first substrate 10 is reflected by the anode electrode 30 toward the second substrate 12.
In some embodiments, the anode electrode 30 may be formed by a transparent conductive material such as indium tin oxide, in which case the anode electrode 30 may be disposed on surfaces of the phosphor layers 26 and the black layers 28 facing the second substrate 12. In other embodiments, the anode electrode 30 may be realized through a structure in which a transparent conductive layer and a metal layer are combined.
A plurality of spacers (not shown) are disposed between the first and second substrates 10 and 12 to resist atmospheric pressure applied to the vacuum vessel to thereby ensure that the gap between the first and second substrates 10 and 12 is uniformly maintained. The spacers are disposed corresponding in position to the black layers 28 so as not to block the phosphor layers 26.
The light emission device is driven by applying predetermined voltages to the cathode electrodes 14, the gate electrodes 18, and the anode electrode 30. For example, either the cathode electrodes 14 or the gate electrodes 18 function as scan electrodes receiving a scan driving voltage, and the other ones of the cathode electrodes 14 or the gate electrodes 18 function as data electrodes receiving a data driving voltage. Further, the anode electrode 30 receives a voltage, for example, a positive direct current voltage of a few hundred to a few thousand volts, required for the acceleration of electron beams.
As a result, electric fields are formed around the electron emission regions 24 at the pixels where a voltage difference between the cathode and gate electrodes 14, 18 is equal to or greater than a threshold value so that electrons are emitted from the electron emission regions 24. The emitted electrons are attracted by the high voltage applied to the anode electrode 30 to thereby collide with and illuminate the phosphor layers 26 of the corresponding pixels.
In the aforementioned driving process, the electron emission regions 24 receive a current required for electron emission from the conductive layers 22 via the resistive layers 20. During this process, the resistive layers 20 function to make uniform the emission characteristics of the electron emission regions 24. Since the conductive layers 22 maintain a predetermined spacing around a circumference of each of the electron emission regions 24 as described above, a predetermined resistance is continuously provided to each of the electron emission regions 24. Hence, the emission uniformity of the electron emission elements 24 is further enhanced.
In the case where the electron emission regions 24 are formed using a screen-printing process, shrinkage in the electron emission regions 24 may occur during the process. This may result in the partial contact of the electron emission regions 24 with the resistive layers 20. However, since a predetermined resistance is provided to the electron emission regions 24 regardless of where such contact with the resistive layers 20 takes place, the emission uniformity of the electron emission elements 24 is not adversely affected.
Further, if the second openings 221 in the conductive layers 22 are formed in a quadrilateral configuration surrounding respectively the first openings 201 in the resistive layers 20, the electron emission regions 24 have different distances from the conductive layers 20 around the circumferences of the electron emission regions 24. Accordingly, depending on where the electron emission regions 24 contact the resistive layers 20, the resistance values provided to the electron emission regions 24 vary to thereby reduce the emission uniformity.
Further, in this embodiment, the cathode electrodes 14 do not include additional isolation electrodes for the mounting of the electron emission regions 24, and the electron emission regions 24 are directly formed on the resistive layers 20. As a result, the electron emission regions 24 may be more precisely mounted, thereby allowing for the increase in the amount of emitted electrons for each pixel and thus enhancing screen luminance.
In addition, in the light emission device of this embodiment, all of the conductive layers 22 may be used as an effective width excluding where the second openings 221 are formed therein. Hence, a drop in voltage of the cathode electrodes 14 is prevented, and the width of the cathode electrodes 14 may be reduced without encountering any significant difficulties, thereby allowing for a high resolution to be achieved.
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With reference to
Further, the electron emission regions 24 contact the corresponding resistive layers 20′ while filling respectively the first openings 201′, and the conductive layers 22′ maintain a predetermined spacing from the circumferences of the corresponding electron emission regions 24.
In this embodiment, the resistive layers 20′ are disposed between the corresponding conductive layers 22′ and the insulation layer 16. Accordingly, when the insulation layer 16 undergoes high-temperature baking, the metal material forming the conductive layers 22′ is prevented from being diffused from the insulation layer 16, thereby preventing a drop in withstanding voltage characteristics of the insulation layer 16 resulting from such diffusion. Except for the structure of the cathode electrodes 14′ as described above, all other aspects of the second exemplary embodiment are similar to the first exemplary embodiment.
Referring to
With reference to
A plurality of fifth openings 341 are formed in the focusing electrode 34 at locations either corresponding to the respective electron emission regions 24, or corresponding to two or more of the respective electron emission regions 24. As an example of the latter case, two of the fifth openings 341 may be formed for each crossed region of the cathode and gate electrodes 14, 18 such that each row of the electron emission regions 24 in the crossed region is exposed by one of the fifth openings 341.
During operation of the light emission device, the focusing electrode 34 receives 0V or a negative direct current voltage of, for example, several tens of volts, required for electron beam focusing. The electrons passed through the fifth openings 341 are focused to a center of a bundle of electron beams. In
A method of manufacturing the electron emission device 100 of the first exemplary embodiment will now be described.
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Although a linewidth of the conductive layers 22 is slightly reduced through the above over-etching process, the functioning of the conductive layers 22 is only minimally affected. Through the above processes, the cathode electrodes 14 formed of the resistive layers 20 and the conductive layers 22 are completed.
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The electron emission material may be a material selected from the group consisting of carbon nanotubes, graphite, graphite nanofibers, diamonds, diamond-like carbon, fullerene (C60), silicon nanowires, and a combination thereof. Since the electron emission regions 24 are hardened through a rear-surface exposure process as described above, a high degree of adhesivity with the first substrate 10 is realized. Further, the electron emission regions 24 are electrically coupled to the resistive layers 20 through contact therewith, such that the electron emission regions 24 receive current required for electron emission from the conductive layers 22.
An adhesive tape (not shown) may be attached to the electron emission regions 24 as needed, and through an activation process of stripping off the same, a surface of the electron emission material is exposed to thereby enhance emission efficiency.
In the manufacturing method of the exemplary embodiment described above, the conductive layers 22 and the resistive layers 20 are patterned using one mask layer 36 such that alignment error between the conductive layers 22 and the resistive layers 20 is minimized, thereby preventing the occurrence of resistance value differences in the electron emission regions 24. Further, through use of the one mask layer 36, manufacturing is simplified, ultimately reducing the cost of production.
In addition, through use of the rear-surface exposure process during patterning of the sacrificial layer 38, the eightieth openings 381 are aligned respectively with the first openings 201, thereby resulting in center axes of the electron emission regions 24 corresponding precisely and respectively with center axes of the first openings 201.
Furthermore, although the electron emission regions 24 may shrink during baking to thereby only partially contact the resistive layers 20, through the structure of the cathode electrodes 14, the electron emission regions 24 are provided with a uniform resistance, thereby enhancing the emission uniformity of the electron emission regions 24.
In the electron emission device 100 made using the manufacturing method of the exemplary embodiment, the central axes of the first openings 201 in the resistive layers 20 are spaced apart from the central axes of the second openings 221 in the conductive layers 22 by 0.5 μm or less.
A manufacturing method for an electron emission device according to the second exemplary embodiment of the present invention will now be described.
Referring to
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The over-etching of the conductive layers 22′ is performed through a wet-etching process, and the size of the second openings 221′ is controlled by adjusting the etching time. Although a linewidth of the conductive layers 22′ is slightly reduced through the over-etching process, the functioning of the conductive layers 22′ is only minimally affected. Through the above processes, the cathode electrodes 14′ formed of the resistive layers 20′ and the conductive layers 22′ are completed.
The subsequent formation of the insulation layer 16, the gate electrodes 18, and the electron emission regions 24 is similar to that described above with respect to the manufacture of the first exemplary embodiment. The completed electron emission device 300 of the second exemplary embodiment is shown in
Although exemplary embodiments of the present invention have been described in detail hereinabove, it should be clearly understood that many variations and/or modifications of the basic inventive concept taught herein still fall within the spirit and scope of the present invention, as defined by the appended claims and their equivalents.
Number | Date | Country | Kind |
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10-2006-0054921 | Jun 2006 | KR | national |