Patent Application
20060238108
This application claims priority to and the benefit of Korean Patent Application No. 10-2005-0016859, filed on Feb. 28, 2005, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to an electron emission device, and in particular, to an electron emission device which has an improved insulation structure disposed on a substrate between driving electrodes to insulate them from each other.
2. Description of Related Art
Generally, electron emission devices are classified into those using hot cathodes as the electron emission source, and those using cold cathodes as the electron emission source. There are several types of cold cathode electron emission devices, including a field emitter array (FEA) type, a surface-conduction emission (SCE) type, a metal-insulator-metal (MIM) type, and a metal-insulator-semiconductor (MIS) type.
The MIM-type electron emission device has an election emission region with a metal-insulator-metal (MIM) structure, and the MIS-type electron emission device has an electron emission region with a metal-insulator-semiconductor (MIS) structure. When voltages are applied to the two metals or the metal and the semiconductor on either side of the insulator, electrons migrate from the high electric potential metal or semiconductor to the low electric potential metal, and are accelerated.
The SCE-type electron emission device includes first and second electrodes formed on a substrate while facing each other, and a conductive thin film disposed between the first and the second electrodes. Micro-cracks are made at the conductive thin film to form electron emission regions. When voltages are applied to the electrodes while making the electric current flow to the surface of the conductive thin film, electrons are emitted from the electron emission regions.
The FEA-type electron emission device is based on the principle that when a material having a low work function or a high aspect ratio is used as an electron emission source, electrons are easily emitted from the material due to the electric field in a vacuum atmosphere. A front sharp-pointed tip structure based on molybdenum (Mo) or silicon (Si), or a layer formed with a carbonaceous material, such as carbon nanotube, graphite and/or diamond-like carbon, has been developed to be used as an electron emission region of the FEA-type electron emission device.
Although the electron emission devices are differentiated in their specific structure depending upon the types thereof, they all basically have first and second substrates forming a vacuum vessel (or a vacuum chamber). Electron emission regions are formed on the first substrate together with driving electrodes for controlling the electron emission of the electron emission regions. Phosphor layers are formed on the second substrate together with an anode electrode for effectively accelerating the electrons emitted from the first substrate toward the phosphor layers to thereby emit light and/or display an image.
With the FEA-type electron emission device, cathode and gate electrodes are formed on the first substrate as the driving electrodes. The cathode electrodes are electrically connected to the electron emission regions to supply electric currents to the electron emission regions. Electric fields are formed around the electron emission regions using a voltage difference between the gate electrodes and the cathode electrodes, thereby inducing the electron emission. The cathode and gate electrodes are insulated from each other by an insulating layer disposed therebetween.
With the FEA-type electron emission device, the insulating layer may be formed either with a thickness of 1 μm or less using a process referred to as a thin film process, such as a deposition process; or with a thickness of 1 μm or more using a process referred to as a thick film process, such as a screen printing process, a doctor blade process, and/or a laminating process.
In the thin film process case, a micro-pixel may be easily formed. However, with the thin insulating layer formed through the thin film process, as the height of the gate electrodes with respect to the electron emission regions is lowered (due the thinness of the insulating layer formed through the thin film process), an electric field due to a high voltage applied to the anode electrode (referred to hereinafter simply as an anode electric field) may directly influence the electron emission regions.
Accordingly, in the above thin film process case, electrons may be emitted from the electron emission regions to pixels that should have been turned off with the driving of the electron emission device due to the influence of the anode electric field, thereby emitting unwanted light through the phosphor layers of the pixels. Consequently, in the electron emission device with the thin insulating layer formed through the thin film process, a high voltage should not be applied to the anode electrode, thereby limiting the intensity of a screen luminance.
In the thick film process case, the gate electrodes may be formed at a plane higher than the electron emission regions to thereby reduce the spread of electron beams so that the mis-operation of the device due to the anode electric field can be prevented, but the thick insulating layer formed through the thick film process can result in the formation of a parasitic capacitance between the cathode electrodes and the gate electrodes due to the high dielectric constant of the insulating layer. Therefore, in the electron emission device with the thick insulating layer, the driving signals can be easily distorted due to the parasitic capacitance of the thick insulating layer so that it becomes difficult to correctly drive the respective pixels.
In one exemplary embodiment of the present invention, there is provided an electron emission device which has a thick insulating layer to electrically insulate the driving electrodes from each other in an appropriate manner, and to inhibit the signal distortion due to a parasitic capacitance of the insulating layer, thereby enhancing the electrical operation characteristic of the electron emission device.
In one embodiment, the electron emission device includes first and second substrates facing each other with a predetermined distance therebetween, and an electron emission region formed on the first substrate. First and second electrodes are placed on the first substrate while being insulated from each other to control an electron emission of the electron emission region. An insulating layer is disposed between the first and second electrodes. An anode electrode is formed on the second substrate. A phosphor layer is formed on a surface of the anode electrode. The insulating layer has a multiple-layered structure including at least two layers differing from each other in electro-physical property.
The insulating layer has at least two layers of the insulating layer differing from each other in specific resistance. The insulating layer has a first layer, and a second layer formed on a surface of the first layer, the second layer having a second specific resistance, the first layer having a first specific resistance, the second specific resistance being lower than the first specific resistance.
The insulating layer has a thickness of 2 μm or more, and the second layer has a specific resistance from 105 to 1012 Ωcm. The thickness of the second layer is established to be at most ½ the total thickness of the insulating layer.
In another embodiment, the electron emission device includes first and second substrates facing each other with a distance therebetween, and first, second and third electrodes formed on the first substrate while being placed at different planes. An electron emission region is electrically connected to the first electrode. A lower insulating layer is disposed between the first and second electrodes. An upper insulating layer is disposed between one of the first and second electrodes and the third electrode. A phosphor layer is formed on the second substrate. An anode electrode is formed on a surface of the phosphor layer. Each of the lower insulating layer and the upper insulating layer has a multiple-layered structure including at least two layers differing from each other in electro-physical property.
The at least two layers of each of the lower insulating layer and the upper insulating layer differ from each other in specific resistance. That is, each of the lower insulating layer and the upper insulating layer has a first layer and a second layer formed on a surface of the first layer, the second layer having a second specific resistance, the first layer having a first specific resistance, the second specific resistance being lower than the first specific resistance. The second layer of the upper insulating layer is in one embodiment placed on an upper surface of the first layer of the upper insulating layer.
Each of the lower insulating layer and the upper insulating layer has a thickness of 2 μm or more. Each of the second layer of the lower insulating layer and the second layer of the upper insulating layer has a specific resistance from 105 to 1012 Ωcm. The thickness of the second layer of the lower insulating layer is established to be at most ½ the total thickness of the lower insulating layer, and the thickness of the second layer of the upper insulating layer is established to be at most ½ the total thickness of the upper insulating layer.
In the present application, when a first part is referred to as being on a second part, the first part may be directly on the second part or indirectly on the second part via a third part.
As shown in
A plurality of cathode electrodes 6 are arranged on the first substrate 2 as first electrodes. The cathode electrodes 6 are stripe-patterned in a first direction of the first substrate 2, while being spaced apart from each other with a distance therebetween. An insulating layer 8 is formed on the entire surface of the first substrate 2 while covering the cathode electrodes 6.
A plurality of gate electrodes 10 are formed on the insulating layer 8 as second electrodes. The gate electrodes 10 are stripe-patterned in a second direction, perpendicular to the first direction of the cathode electrodes 6, while being spaced apart from each other with a distance therebetween.
In this embodiment, when the crossed regions of the cathode and the gate electrodes 6 and 10 are defined as pixel regions, one or more openings 12 are formed at the gate electrode 6 and the insulating layer 8 per the respective pixel regions while partially exposing the cathode electrode 6. Electron emission regions 14 are formed on the cathode electrodes 6 within the openings 12. The electron emission regions 14 are electrically connected to the cathode electrodes 6.
The electron emission regions 14 are formed with a material for emitting electrons under the application of an electric field, such as a carbonaceous material and/or a nanometer-sized material. In one embodiment, the electron emission regions 14 are formed using carbon nanotube, graphite, graphite nanofiber, diamond, diamond-like carbon, C60, and/or silicon nanowire, by way of screen-printing, direct growth, chemical vapor deposition, and/or sputtering.
It is illustrated in
Referring still to
With the difference in specific resistance, one of the first and second layers 8a and 8b can substantially function as an insulating layer, while the other layer can function as a resistance layer with a specific resistance lower than that of the former layer.
Specifically, in one embodiment, the insulating layer 8 has the first layer 8a formed with a common insulating material such as glass frit, and the second layer 8b formed on the first layer 8a with a material having a specific resistance from 105 to 1012 Ωcm. The first layer 8a is substantially functioning as the insulating layer, and the second layer 8b lowers the capacitance of the insulating layer 8 at the crossed regions of the cathode and the gate electrodes 6 and 10 due to the specific resistance characteristic thereof.
The specific resistance of the second layer 8b is considerably higher than that of the conductive material forming the gate electrodes 10, and the electrical insulation of the gate electrodes 10 contacting the second layer 8b is achieved to be at the same degree as with the conventional insulating layer. For reference, with the main materials for the gate electrodes 10 being formed with aluminum (Al) and/or molybdenum (Mo), aluminum has a specific resistance of 2.65×10−6 Ωcm, and molybdenum has a specific resistance of 5.7×10−6 Ωcm.
The insulating layer 8 is formed through a thick film process, such as a screen printing process, a doctor blade process, and/or a laminating process. The insulating layer 8 in one embodiment has a thickness of 1 μm or more, and more particularly has a thickness of 2 μm or more. The thickness of the second layer 8b functions as a resistance layer, and is in one embodiment established to be at most ½ the total thickness of the insulating layer 8 (e.g., 1 μm or less) such that the second layer 8b does not distort the insulation characteristic of the insulating layer 8.
With the above-identified thickness of the insulating layer 8, the gate electrodes 10 have a sufficient height with respect to the electron emission regions 14, and during the driving of the electron emission device, the gate electrodes 10 partially shield the influence of the anode electric field to the electron emission regions 14.
As shown in
Referring now back to
Phosphor layers 16 and black layers 18 are formed on a surface of the second substrate 4 facing the first substrate 2. An anode electrode 20 is formed on the phosphor layers 16 and the black layers 18 with a metallic material, such as aluminum. The anode electrode 20 receives a high voltage required for accelerating the electron emission structure toward the phosphor layers 16 electron beams, and reflects the visible rays radiated from the phosphor layers 16 to the first substrate 2 toward the second substrate 4, thereby further heightening the screen luminance.
Alternatively, the anode electrode may be formed with a transparent conductive material, such as indium tin oxide (ITO), instead of the metallic material. In this case, the anode electrode (not shown) is placed on the surface of the phosphor layers and the black layers facing the second substrate. The electrode being partitioned into a plurality of separate portions with a predetermined pattern, or formed on the entire surface at the second substrate.
The first and second substrates 2 and 4 are sealed with each other with a predetermined distance therebetween using a sealant (not shown) such that the gate electrodes 10 face the anode electrode 20. The inner space between the first and second substrates 2 and 4 is exhausted to be in a vacuum state, thereby constructing an electron emission device. A plurality of spacers 22 are arranged at the non-light emission area between the first and second substrates 2 and 4 to space them from each other with the predetermined distance.
The above-structured electron emission device is driven by supplying predetermined voltages to the cathode electrodes 6, the gate electrodes 10, and the anode electrode 20 from the outside. For instance, a plus (+) direct current (DC) voltage of several hundred to several thousand volts is applied to the anode electrode 20. Scan signals are applied to the gate electrodes 10, and data signals are applied to the cathode electrodes 6. The turning on and the turning off of the respective pixels are controlled using the voltage difference between the cathode and gate electrodes 6 and 10.
Electric fields are formed around the electron emission regions 14 at the pixels where the voltage difference between the cathode and gate electrodes 6 and 10 exceeds a threshold value, and electrons are emitted from these electron emission regions 14. The emitted electrons are attracted by the high voltage applied to the anode electrode 20, and are directed to collide against the phosphor layers 16 at the relevant pixels to thereby emit light.
In the electron emission device according to the first embodiment and with the above driving process, as the insulating layer 8 has the second layer 8b with the specific resistance from 105 to 1012 Ωcm, the capacitance inevitably formed at the insulating layer 8 corresponding to the crossed regions of the cathode and gate electrodes 6 and 10 is lowered, thereby inhibiting a distortion of the driving signals. As a result, with the electron emission device according to the present embodiment, the respective pixels are correctly driven, thereby enhancing the display characteristic.
As shown in the drawings, with the electron emission device according to the third embodiment of the present invention, gate electrodes 10′ being a plurality of second electrodes, an insulating layer 8 having a double-layered structure with first and second layers 8a and 8b, and cathode electrodes 6′ being a plurality of first electrodes are sequentially formed on a first substrate 2.
The gate and cathode electrodes 10′ and 6′ are stripe-patterned and perpendicular to each other, and electron emission regions 14′ are formed at the one-sided periphery of a cathode electrode 6′ corresponding to respective pixel regions such that at least one lateral side of an electron emission region 14′ is surrounded by the cathode electrode 6′.
Counter electrodes 24 are formed on the first substrate 2 to pull the electric field of the gate electrodes 10′ through the insulating layer 8. The counter electrodes 24 are spaced apart from the electron emission regions 14′ with a distance therebetween while being disposed between the cathode electrodes 6′, and are electrically connected to the gate electrodes 10′ through holes (or vias) 26 formed at the insulating layer 8. Similar to the electron emission regions 14′, the counter electrodes 24 are provided corresponding to the pixel regions defined on the first substrate 2.
With the electron emission device at
Accordingly, electric fields are formed around the electron emission regions 14′ at the pixels where the voltage difference between the cathode and the gate electrodes 6′ and 10′ exceeds a threshold value, from the bottom of the electron emission regions 14′ where the gate electrodes 10′ are located, and from the lateral sides of the electron emission regions 14′ where the counter electrodes 24 are located. Electrons are emitted from the electron emission regions 14′, and attracted by a high voltage applied to the anode electrode 20, thereby colliding against the phosphor layers 16 at the relevant pixels.
In the electron emission device of
As shown in the drawings, the basic structural components of the electron emission device according to the fifth embodiment of the present invention are substantially the same as those shown and/or described for the first embodiment except that a focusing electrode 28 is formed over the gate electrodes 10 as a third electrode. An insulating layer 30 is disposed between the gate electrodes 10 and the focusing electrode 28 to electrically insulate them from each other. An insulating layer 8 disposed between the cathode and gate electrodes 6 and 10 is hereinafter referred to as a lower insulating layer, and the insulating layer 30 disposed between the gate and focusing electrodes 10 and 28 is hereinafter referred to as the upper insulating layer.
Openings 32 are formed at the focusing electrode 28 and the upper insulating layer 30 to expose the electron emission regions 14 on the first substrate 2. The openings 32 are provided to the pixel regions, respectively, such that the focusing electrode 28 collectively focuses the electrons emitted at each pixel region. The focusing electrode 28 may be formed on the entire surface of the first substrate 2, or partitioned into a plurality of separate portions with a predetermined pattern. In the latter case, the illustration thereof is not shown.
In this embodiment, the upper insulating layer 30 also has a double-layered structure with first and second layers 30a and 30b that differ from each other in specific resistance. The first layer 30a is formed with a common insulating material such as glass frit, and the second layer 30b in one embodiment has a specific resistance from 105 to 1012 Ωcm. Therefore, the first layer 30a substantially functions as an insulating layer disposed between the gate and focusing electrodes 10 and 28, and the second layer 30b lowers the capacitance of the upper insulating layer 30, thereby inhibiting a signal distortion.
The upper insulating layer 30 is also formed through a thick film process, such as a screen printing process, a doctor blade process, and/or a laminating process. The upper insulating layer 30 in one embodiment has a thickness of 1 μm or more, and more particularly has a thickness of 2 μm or more. The thickness of the upper insulating layer 30 (D1, as shown in
In addition, the thickness of the second layer 30b of the upper insulating layer 30 is in one embodiment established to be at most ½ the total thickness of the upper insulating layer 30.
Furthermore, the second layer 30b of the upper insulating layer 30 is in one embodiment placed over the first layer 30a. In this case, the focusing electrode 28 is electrically thickened due to the low specific resistance characteristic of the second layer 30b as compared to the first layer 30a. Therefore, the focusing capacity of the focusing electrode 28 is heightened, and the influence of the anode electric field with respect to the electron emission regions 14 is effectively shielded, thereby constructing a high-efficiency electron emission device. For this purpose, the second layer 30b of the upper insulating layer 30 has a thickness larger than the second layer 8b of the lower insulating layer 8.
Meanwhile, as shown in
A minus (−) direct current (DC) voltage of several to several ten volts is applied to the focusing electrode 28 to focus the electrons emitted from the electron emission regions 14 during the operation of the electron emission device, thereby minimizing the spreading of electron beams.
As shown in the drawings, the basic structural components of the electron emission device according to the seventh embodiment of the present invention are substantially the same as those shown and/or described for the third embodiment except that a focusing electrode 28 is formed over the cathode electrodes 6′ as a third electrode. An upper insulating layer 30 is disposed between the cathode electrodes 6′ and the focusing electrode 28 to electrically insulate them from each other.
The upper insulating layer 30 and the focusing electrode 28 also have openings 32 exposing the electron emission regions 14′ on the first substrate 2. The openings 32 are provided corresponding to the electron emission regions 14′, respectively. The focusing electrode 28 may be formed on the entire surface of the first substrate 2, or partitioned into a plurality of separate portions with a predetermined pattern. In the latter case, the illustration thereof is not shown.
The upper insulating layer 30 has a double-layered structure with first and second layers 30a and 30b that differ from each other in specific resistance. The first layer 30a is formed with a common insulating material such as glass frit, and the second layer 30b in one embodiment has a specific resistance from 105 to 1012 Ωcm. Therefore, the first layer 30a substantially functions as an insulating layer disposed between the cathode and focusing electrodes 6′ and 28, and the second layer 30b lowers the capacitance of the upper insulating layer 30, thereby inhibiting a signal distortion.
An insulating layer 8 is disposed between the gate and the cathode electrodes 10′ and 6′ and is hereinafter referred to as a lower insulating layer. Each of the lower and upper insulating layers 8 and 30 has a thickness of 1 μm or more, and more particularly has a thickness of 2 μm or more. The thickness of the upper insulating layer 30 is in one embodiment established to be larger than the thickness of the lower insulating layer 8 such that the focusing electrode 28 has a sufficient height with respect to the electron emission regions 14′.
In order for the focusing electrode 28 to be electrically thickened, the second layer 30b of the upper insulating layer 30 is placed over the first layer 30a of the upper insulating layer 30. The thickness of the second layer 30b of the upper insulating layer 30 is in one embodiment established to be at most ½ the total thickness of the upper insulating layer 30, and the thickness of the second layer 8b is in one embodiment established to be at most ½ the total thickness of the lower insulating layer 8.
As shown in
As described above, in an electron emission device according to the present invention, a capacitance of an insulating layer is lowered at crossed regions of first and second electrodes and/or at crossed regions of the second electrodes and a third electrode, thereby inhibiting a distortion of driving signals. Accordingly, with the electron emission device, the respective pixels of the electron emission device are correctly driven, thereby enhancing the display characteristics.
In case a second layer of an insulating layer is placed over a first layer thereof, a problematic accumulation of electrons at the insulating layer can be prevented, and the mis-discharging pursuant thereto can also be prevented. Furthermore, in case a focusing electrode is provided, and a second layer of an upper insulating layer is placed over a first layer thereof, the focusing electrode is electrically thickened to efficiently shield the electron emission regions from the influence of the anode electric field, thereby enabling the construction of a high-efficiency electron emission device.
Also, while the certain embodiments of the present invention are explained above in relation to the FEA-type electron emission device where the electron emission regions are formed with a material emitting electrons when an electric field is applied under a vacuum atmosphere, the structure of the present invention is not limited to the FEA-type electron emission device, and may be applied to other-type electron emission devices where the driving electrodes are placed at different planes while an insulating layer is interposed between at least two of the different planes.
While the invention has been described in connection with certain exemplary embodiments, it is to be understood by those skilled in the art that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications included within the spirit and scope of the appended claims and equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2005-0016859 | Feb 2005 | KR | national |
