Patent Application
20090295690
The present invention relates to an electronic circuit and a panel having the same, and more particularly to an electronic circuit which is capable reducing a dispersion of luminances in a panel, and the panel having the same.
In recent years, a planar self-emission type panel using an organic Electro Luminescent (EL) device as a light emitting element (hereinafter referred to as “an EL panel”) has been actively developed. This EL panel, for example, is described in Japanese Patent Laid-Open Nos. 2003-255856, 2003-271095, 2004-133240, 2004-029791, and 2004-093682.
In the existing EL panel, it is feared that there is a dispersion of luminances in pixels, and thus the dispersion of the luminances is seen as non-uniformity by an eye of a user. This is a problem involved in the existing EL panel.
The embodiment of present invention has been made in the light of such circumstances, and it is therefore desirable to provide an electronic circuit which is capable reducing a dispersion of luminances in a panel, and the panel having the same.
In order to attain the desire described above, according to an embodiment of the present invention, there is provided an electronic circuit including: a light emitting element, having diode characteristics, for emitting a light in accordance with a drive current; a sampling transistor for sampling a video signal; a driving transistor for supplying the drive current to the light emitting element; and a hold capacitor for holding therein a predetermined potential, the hold capacitor being connected to each of an anode side of the light emitting element, and a gate of the driving transistor; in which a laminated portion of a first metallic layer serving as a gate of the sampling transistor, and a second metallic layer serving as a source of the sampling transistor is formed so as to have an area equal to or smaller than a predetermined area.
According to another embodiment of the present invention, there is provided a panel including a pixel circuit having: a light emitting element, having diode characteristics, for emitting a light in accordance with a drive current; a sampling transistor for sampling a video signal; a driving transistor for supplying the drive current to the light emitting element; and a hold capacitor for holding therein a predetermined potential, the hold capacitor being connected to each of an anode side of the light emitting element, and a gate of the driving transistor; in which in the pixel circuit, a laminated portion of a first metallic layer serving as a gate of the sampling transistor, and a second metallic layer serving as a source of the sampling transistor is formed so as to have an area equal to or smaller than a predetermined area.
As set forth hereinabove, according to embodiments of the present invention, it is possible to suppress the dispersion of the luminances in the panel.
Firstly, in order to facilitate understanding of embodiments of the present invention and to make a background of the embodiments of the present invention clear, a configuration and an operation as a basis of a panel using an organic EL device (hereinafter referred to as “an EL panel”) will be described with reference to
The EL panel 100 shown in
In addition, the EL panel also has M scanning lines WSL10-1 to WSL10-M, M power source lines DSL10-1 to DSL10-M, and N video signal lines DTL10-1 to DTL10-N.
It is noted that when in the following description, there is no need for especially distinguishing the scanning lines WSL10-1 to WSL10-M, the video signal lines DTL10-1 to DTL10-N, the pixels 101-(1, 1) to 101-(N, M), or the power source lines DSL10-1 to DSL10-M from one another, they are simply referred to as the scanning lines WSL10, the video signal lines DTL10, the pixels 101, or the power source lines DSL10, respectively.
The pixels 101-(1, 1) to 101-(N, 1) belonging to the first row of the pixels 101-(1, 1) to 101-(N, M) are connected to the write scanner 104 and the power source scanner 105 through the scanning line WSL10-1 and the power source line DSL10-1, respectively. In addition, the pixels 101-(1, M) to 101-(N, M) belonging to the M-th row of the pixels 101-(1, 1) to 101-(N, M) are connected to the write scanner 104 and the power source scanner 105 through the scanning line WSL10-M and the power source line DSL10-M, respectively. This connection form in the row direction also applies to other pixels 101 disposed in the row direction of the pixels l01-(1, 1) to 101-(N, M).
In addition, the pixels 101-(1, 1) to 101-(1, M) belonging to the first column of the pixels 101-(1, 1) to 101-(N, M) are connected to the horizontal selector 103 through the video signal line DTL10-1. In addition, the pixels 101-(N, 1) to 101-(N, M) belonging to the N-th column of the pixels 101-(1, 1) to 101-(N, M) are connected to the horizontal selector 103 through the video signal line DTL10-N. This connection form in the column direction also applies to other pixels 101 disposed in the column direction of the pixels 101-(1, 1) to 101-(N, M).
The write scanner 104 successively supplies a control signal to the scanning lines WSL10-1 to WSL10-M with a horizontal period 1H, thereby scanning the pixels 101 in rows in a line-sequential manner. The power source scanner 105 supplies a power source voltage of a first potential Vcc which will be described later or a second potential Vss which will be described later to the power source lines DSL10-1 to DSL10-M in accordance with the line-sequential scanning. Also, the horizontal selector 103 switches a signal potential Vsig becoming a video signal, and a reference potential Vofs over to each other in each of the horizontal time periods 1H in accordance with the line-sequential scanning, thereby supplying the potential obtained through the switching to video signal lines DTL10-1 to DTL10-N wired in the column direction.
A panel module is configured by adding a driver Integrated Circuit (IC) composed of a source driver and a gate driver to the EL panel 100 configured as shown in
It is noted that as apparent from
The pixel shown in
One of a source 32s and a drain 32d of the drive transistor 32 is connected to an anode of the light emitting element 34, and the other thereof is connected to the power source line DSL10. The storage capacitor 33 is connected between the gate 32g of the driving transistor 32, and the anode of the light emitting element 34. In addition, a cathode of the light emitting element 34 is connected to a wiring 35 set at a predetermined potential Vcat.
In this example, each of the writing transistor 31 and the driving transistor 32 is configured in the form of an N-channel transistor and thus can be manufactured with amorphous silicon. Here, amorphous silicon can be more inexpensively made than low-temperature polysilicon can be made. Therefore, it is possible to greatly reduce a manufacture cost of the entire pixel circuit.
The light emitting element 34 emits a light at a gradation corresponding to a current value Ids supplied thereto. That is to say, the light emitting element 34 functions as an organic EL element as a current light emitting element.
In the pixel 101 configured in the manner as described above, when the writing transistor 31 is turned ON (conduction) in accordance with a control signal supplied thereto from the scanning line WSL10, the storage capacitor 33 accumulates and holds therein the electric charges supplied thereto from the horizontal selector 103 through the video signal line DTL10. That is to say, the predetermined voltage corresponding to the electric charges thus accumulated is held in the storage capacitor 33. The driving transistor 32 receives a current supplied thereto from the power source line DSL10 set at the first potential Vcc, and causes a drive current Ids corresponding to the signal potential Vsig held in the storage capacitor 33 to flow through the light emitting element 34. The predetermined drive current Ids is caused to flow through the light emitting element 34, so that the light emitting element 34 emits a light.
The pixel 101 has a threshold correcting function. The threshold correcting function means a function of causing the storage capacitor 33 to hold therein the voltage corresponding to a threshold voltage Vth of the drive transistor 32. The exercising of the threshold correcting function of the pixel 101 makes it possible to cancel an influence of the threshold voltage Vth of the drive transistor 32 causing the dispersion for each pixel of the EL panel 100.
In addition, the pixel 101 also has a mobility correcting function in addition to the threshold correcting function described above. The mobility correcting function means a function of adding the correction for a mobility μ of the driving transistor 32 to the signal potential Vsig when the signal potential Vsig is held in the storage capacitor 33.
Moreover, the pixel 101 has a bootstrap function as well. The bootstrap function means a function of causing a gate potential Vg to be cooperable with a change in source potential Vs of the driving transistor 32. The exercising of the bootstrap function of the pixel 101 makes it possible to hold a voltage developed across the gate 32g and the source 32s of the driving transistor 32 constant.
It is noted that the threshold correcting function, the mobility correcting function, and the bootstrap function will also be described later with reference to figures such as
In
A time period from the time t1 at end of the emission time period T1 to time t4 is a threshold correction preparing time period T2 for which the gate potential Vg and the source potential Vs of the driving transistor 32 are initialized, thereby preparing for a threshold voltage correcting operation.
For the threshold correction preparing time period T2, the power source scanner 105 switches the potential of the power source line DSL10 from the high potential Vcc over to the low potential Vss at the time t1. Also, the horizontal selector 103 switches the potential of the video signal line DTL10 from the signal potential Vsig over to the reference potential Vofs at time t2. Next, at time t3, the write scanner 104 switches the potential of the scanning line WSL10 from the low potential over to the high potential, thereby turning ON the writing transistor 31. As a result, the gate potential Vg of the driving transistor 32 is reset at the reference potential Vofs, and the source potential Vs of the driving transistor 32 is reset at the low potential Vss of the video signal line DTL10.
A time period from time t4 to time t5 is a threshold correction time period T3 for which the threshold voltage correcting operation is carried out. For the threshold correction time period T3, at the time t4, the power source scanner 105 switches the potential of the power source line DSL10 from the low potential Vss over to the high potential Vcc. As a result, the voltage corresponding to the threshold voltage Vth is written to the storage capacitor 33 connected between the gate 32g and the source 32s of the drive transistor 32.
For a write+mobility correction preparing time period T4 from time t5 to time t7, the potential of the scanning line WSL10 is temporarily switched from the high potential over to the low potential. Also, at time t6 just before the time t7, the horizontal selector 103 switches the potential of the video signal line DTL10 from the reference potential Vofs over to the signal potential Vsig corresponding to the gradation.
Also, for a write+mobility correction time period T5 from the time t7 to time t8, the operation for writing the video signal, and the mobility correcting operation are carried out. That is to say, for the write+mobility correction time period T5 from the time t7 to the time t8, the potential of the scanning line WSL10 is set at the high potential. As a result, the voltage obtained by adding the signal potential Vsig of the video signal to the threshold voltage Vth is written to the storage capacitor 33, and a voltage ΔVμ for mobility correction is subtracted from the voltage held in the storage capacitor 33.
At the time t8 after end of the write+mobility correction time period T5, the potential of the scanning line WSL10 is set at the low potential. Also, for an emission time period T6 at end and after the time t8, the light emitting element 34 emits a light with an emission luminance corresponding to the signal voltage Vsig. The emission luminance of the light emitting element 34 is free from an influence of dispersions of the threshold voltages Vth and the mobilities μ of the drive transistor 23 because the signal potential Vsig is adjusted with the voltage corresponding to the threshold voltages Vth, and the voltage ΔVμ for mobility correction.
It is noted that the bootstrap operation is carried out at the first of the emission time period T6, and as a result, each of the gate potential Vg and the source potential Vs of the driving transistor 32 rises while a gate-to-source voltage Vgs (=Vsig+Vth−Δμ) of the driving transistor 32 is held constant.
In addition, at time t9 after a lapse of predetermined time from the time t8, the potential of the video signal line DTL10 is caused to drop from the signal potential Vsig to the reference potential Vofs. In
In the manner as described above, in the EL panel 100 having the pixel 101 thus configured, it is possible to cause the light emitting element 34 to emit a light without coming under the influence of the dispersions of the threshold voltages Vth and the mobilities μ of the driving transistors 32.
The operation of the pixel 101 will now be described in more detail with reference to
For the emission time period T1, the writing transistor 31 is held in an OFF state (the potential of the scanning line WSL10 is held at the low potential), and the potential of the power source line DSL10 is held at the high potential Vcc. Thus, the driving transistor 32 supplies a drive current Ids to the light emitting element 34. At this time, since the driving transistor 32 is set so as to be operated in a saturated region, the drive current Ids caused to flow through the light emitting element 34 takes a value expressed by Expression (1) in accordance with the gate-to-source voltage Vgs of the driving transistor 32:
Ids=(½)·μ·(W/L)·Cox·(Vgs−Vth)2 (1)
where μ is the mobility, W is a gate width of the driving transistor 32, L is a gate length of the driving transistor 32, Cox is a capacitance of a gate oxide film per unit area in the driving transistor 32, Vgs is the voltage developed across the gate 32g and the source 32s (gate-to-source voltage) of the driving transistor 32, and Vth is the threshold voltage of the driving transistor 32. It is noted that the saturated region means a state fulfilling a condition of (Vgs−Vth<Vds) (Vds is a voltage developed across the source 32s and the drain 32d of the driving transistor 32).
Also, at the first time t1 of the threshold correction preparing time period T2, as shown in
Next, as shown in
Also, when as shown in
Here, the light emitting element 34 can be equivalenty expressed in the form of a parallel combination of a diode 34A and a storage capacitor 34B having a parasitic capacitance Cel parasitized thereon. Thus, the current caused to flow through the driving transistor 32 is used to charge each of the storage capacitors 33 and 34B with the electricity under the condition that a leakage current of the light emitting element 34 is considerably smaller than the current caused to flow through the drive transistor 32 (under the condition that the relationship of (Vel≦Vcat+Vthel) is fulfilled). The anode potential Vel of the light emitting element 34 (the source potential Vs of the driving transistor 32), as shown in
After that, at the time t5, as shown in
After at the time t6 of the subsequent write+mobility correction preparing time period T4, the horizontal selector 103 switches the potential of the video signal line DTL10 from the reference potential Vofs over to the signal potential Vsig corresponding to the gradation (refer to
The threshold correcting operation for the driving transistor 32 has already been completed. Therefore, the term of (Vgs−Vth)2 in the right-hand side member of Expression (1) is expressed by Expression (2):
As a result, since the influence of the term of the threshold voltage Vth is removed, the drive current Ids which the driving transistor 32 caused to flow reflects the mobility μ of the driving transistor 32. Specifically, as shown in
The potential of the scanning line WSL10 is set at the low potential at the time t8, thereby turning OFF the writing transistor 31. As a result, the operation of the pixel 101 for the write+mobility correction time period T5 is completed, and then enters the emission time period T6 (refer to
For the emission time period T6, the gate-to-source voltage Vgs of the driving transistor 32 is held constant. Thus, the driving transistor 32 supplies the constant current Ids′ to the light emitting element 34, the anode potential Vel of the light emitting element 34 rises up to a voltage Vx with which the current, that is, the constant current Ids′ is caused to flow through the light emitting element 34. As a result, the light emitting element 34 emits a light. When the source potential Vs of the driving transistor 32 rises, the gate potential Vg of the driving transistor 32 also rises in conjunction with the rising of the source potential Vs of the driving transistor 32 based on the bootstrap function of the storage capacitor 33.
When the emission time period becomes long, a potential at a point B shown in
As described above, in the EL panel 100, shown in
As a result, with the display device using the EL panel 100 shown in
Here, the primary factor causing the problem, in the related art, which was described in the opening of the paragraph of “SUMMARY OF THE INVENTION” will be described with reference to
At least a first metallic layer M1, and a second metallic layer M2 are laminated in the order from the lower side on the substrate shown in
On the substrate shown in
As shown in
The second metallic layer M2 on the drain 31d side is formed so as to have a rectangular shape. Also, the second metallic layer M2 on the source 31s side is formed so as to have an L-like shape. In this case, the second metallic layer M2 on the drain 31d side, and the second metallic layer M2 on the source 31s side are disposed on a part of the first metallic layer M1 forming the gate 31g of the writing transistor 31 so that each of long sides of the rectangle, and a long segment portion of the L-like shape are approximately parallel with each other.
Moreover, in the substrate shown in
From the comparison of the flow chart shown in
An equivalent circuit of the pixel 101 at the time point indicated by the circular frame 51 shown in
where Cws is a parasitic capacitance between the source 31s and the gate 31g of the writing transistor 31 (hereinafter referred to as “a writing transistor parasitic capacitance”), Cel is a parasitic capacitance of the storage capacitor 34B in the light emitting element 34 (hereinafter referred to as “an organic EL capacitance”), Cs is a capacitance of the storage capacitance 33, Cgs is a parasitic capacitance between the gate 32g and the source 32s of the driving transistor 32 (hereinafter referred to as “a driving transistor gate-to-source parasitic capacitance”), and Cgd is a parasitic capacitance between the gate 32g and the drain 32d of the driving transistor 32 (hereinafter referred to as “a driving transistor gate-to-drain parasitic capacitance”).
As shown in a right-hand side member of Expression (3), it is understood that a parameter most influenced by the feedthrough voltage drop amount is one of a denominator, that is, the writing transistor parasitic capacitance Cws.
As shown in
Here, a line width d1 of each of the long sides of the overlapping portion, that is, the rectangle-shaped portion in the writing transistor 31 is approximately identical to that in the writing transistor 31 in each of the pixels 101-(1, 1) to 101-(N, M) composing the EL panel. On the other hand, a line width ds of each of short sides disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel. The reason for this dispersion is because the exposure processing described above for any one of the pixels 101-(1, 1) to 101-(N, M) composing the EL panel is carried out independently of the exposure processing for other pixels. That is to say, since the first metallic layer M1 and the second metallic layer M2 are formed for each of the pixels 101-(1, 1) to 101-(N, M) composing the EL panel, it is impossible to perfectly suppress the dispersion of differences ds in short sides between the first metallic layers M1 and the second metallic layers M2 (hereinafter referred to as “line width differences ds”).
That is to say, the line width difference ds disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel. That is to say, an area of a portion, overlapping the first metallic layer M1 forming the gate 31g, of the second metallic layer M2 on the source 31s disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel. Thus, the writing transistor parasitic capacitance Cws disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel. As a result, as apparent from Expression (3), the feedthrough voltage drop amount Vfs disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel.
Moreover, when the feedthrough voltage drop amount Vfs disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel, the luminance disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel accordingly. In this case, when a difference in luminance between one pixel and any of the pixels adjacent thereto is 1% or more, there is caused the problem that a user who sees the entire EL panel as one image visually recognizes this luminance difference as non-uniformity. That is to say, there is caused the problem described in the opening of the paragraph of “SUMMARY OF THE INVENTION.”
In other words, the primary factor causing the problem described in the opening of the paragraph of “SUMMARY OF THE INVENTION” is that the writing transistor parasitic capacitance Cws disperses in the pixels 101-(1, 1) to 101-(N, M) composing the EL panel.
In order to solve the problem as described above, the inventor of the embodiment of the present invention has arrived at a technical idea that the area of the second metallic layer M2 on the source 31s side of the writing transistor 31 is made small as compared with the case of the related art, more properly, a technical idea that the area of the portion, overlapping the first metallic layer M1 forming the gate 31g of the writing transistor 31, of the second metallic layer M2 on the source 31s side of the writing transistor 31 is made small as compared with the case of the related art.
The inventor of the embodiment of the present invention has invented a layout shown in
That is to say,
In order to clarify the feature of the substrate of the embodiment of the present invention shown in
From comparison of the substrate of the embodiment of the present invention shown in
In this case, any of the writing transistor parasitic capacitances Cws in the pixel 101-(1, 1) to 101-(N, M) composing the EL panel is smaller in the substrate of the embodiment of the present invention shown in
From comparison of a circular frame 53 shown in FIG. 18 with the circular frame 51 in
Here, the fact that any of the writing transistor parasitic capacitances Cws in the pixel 101-(1, 1) to 101-(N, M) composing the EL panel is smaller in the substrate of the embodiment of the present invention shown in
From this, the fact that the degree of the dispersion of the writing transistor parasitic capacitances Cws in the pixel circuits 101-(1, 1) to 101-(N, M) composing the EL panel becomes small results in that the feedthrough voltage drop amounts in the pixel circuits 101-(1, 1) to 101-(N, M) composing the EL panel leads to a decrease in degree of the dispersion. As a result, the degree of the dispersion of the luminances in the pixel circuits 101-(1, 1) to 101-(N, M) composing the EL panel also decreases.
Here, when the degree of the dispersion of the luminances can be reduced so that a difference in luminance between one pixel and any of the pixels adjacent thereto is made smaller than 1%, the user who sees the entire EL panel as one image can visually recognize the image having no non-uniformity occurring therein. That is to say, it is possible to solve the problem described in the opening in the paragraph of “SUMMARY OF THE INVENTION.”
In other words, in order to solve the problem described in the opening in the paragraph of “SUMMARY OF THE INVENTION,” all that is required is that the area of the portion, overlapping the first metallic layer M1 forming the gate 31g of the writing transistor 31, of the second metallic layer M2 on the source 31s side is made smaller than the predetermined area allowing the difference in luminance between one pixel and any of the pixels adjacent thereto to be made about 1%.
Here, with regard to a technique for reducing the area of the overlapping portion, there are expected a technique for making the line width difference ds (refer to
Next, an EL panel according to an embodiment of the present invention will be described.
The EL panel includes the pixel circuit (pixel) 101 having the light emitting element 34, having the diode characteristics, for emitting a light in accordance with the drive current, the writing transistor 31 for sampling the video signal, the driving transistor 32 for supplying the drive current to the light emitting element 34, and the storage capacitor 33 for holding therein the predetermined potential. The storage capacitor 33 is connected to each of the anode side of the light emitting element 34, and the gate of the driving transistor 32. In this case, in the pixel circuit 101, the laminated portion of the first metallic layer M1 serving as the gate of the writing transistor 31, and the second metallic layer M2 serving as the source of the writing transistor 31 is formed so as to have the area equal to or smaller than the predetermined area.
In addition, preferably, in the second metallic layer M2, a first portion serving as the drain of the writing transistor 31 is formed apart from a second portion serving as the source of the writing transistor 31, and the second portion is formed in a way that the length of the line thereof facing the first portion becomes equal to or smaller than the given value.
The embodiments of the present invention are by no means limited to the embodiments described above, and thus various changes can be made without departing the gist of the present invention.
The present application contains subject matter related to that disclosed in Japanese Priority Patent Application JP 2008-142438 filed in the Japan Patent Office on May 30, 2008, the entire content of which is hereby incorporated by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factor in so far as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2008-142438 | May 2008 | JP | national |
