Claims
- 1. An electronic circuit arrangement for controlling at least one actuator comprising at least one driver circuit with a control input and a resetting input for electrically controlling the actuator as a function of the data which is incoming at the control input, a control unit which is connected at the output end to the resetting input via a resetting line and to the control input of the driver circuit via a control line, and comprising a signal input which is connected internally to the control unit for the external connection of a switching element, the control unit placing the driver circuit in a predefined state when the switching element is activated via the resetting line, wherein the signal input for the switching element is coupled with the resetting input of the driver circuit via a signal path while bypassing the control unit.
- 2. The circuit arrangement as claimed in claim 1, wherein a logic circuit is connected upstream of the resetting input of the driver circuit and is connected at the input end, on the one hand, to the control unit and, on the other hand, to the signal input via the signal path, the resetting input of the driver circuit being able to be optionally activated by means of the control unit and/or the signal input.
- 3. The circuit arrangement as claimed in claim 2, wherein the resetting input of the driver circuit is HIGH active and the logic circuit has an OR gate.
- 4. The circuit arrangement as claimed in claim 2, wherein the resetting input of the driver circuit is LOW active and the logic circuit has an AND gate.
- 5. The circuit arrangement as claimed in claim 1, wherein a delay element is arranged in the signal path bypassing the control unit, between the signal input for the switching element and the resetting input of the driver circuit.
- 6. The circuit arrangement as claimed in claim 5, wherein the delay element has a delay of more than 700 ms.
- 7. The circuit arrangement as claimed in claim 1, wherein the control unit comprises a microcontroller and a monitoring unit which is connected to the microcontroller, the microcontroller being connected at the output end to the control input of the driver circuit via the control line, whereas the monitoring unit is connected at the output end to the driver circuit via the resetting line.
- 8. The circuit arrangement as claimed in claim 7, wherein the microcontroller and the monitoring unit are connected to a databus.
- 9. The circuit arrangement as claimed in claim 8, wherein the databus is an SPI bus.
- 10. The circuit arrangement as claimed in claim 1, wherein the circuit controls the valves and/or the injectors of an injection system of an internal combustion engine.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of International Application No. PCT/DE01/02674 filed Jul. 17, 2001, which designates the United States, which claims priority to German application number DE10036903.0 filed Jul. 28, 2000.
US Referenced Citations (6)
Foreign Referenced Citations (3)
Number |
Date |
Country |
3925881 |
Feb 1991 |
DE |
196 05 606 |
Aug 1997 |
DE |
0 358 972 |
Mar 1990 |
EP |
Non-Patent Literature Citations (1)
Entry |
“Design Techniques for an Intelligent Fuel Injector IC”; A. Marshall, J. Devore and W. Grose; Texas Instruments Inc., Dallas, TX; 1992. |
Continuations (1)
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Number |
Date |
Country |
Parent |
PCT/DE01/02674 |
Jul 2001 |
US |
Child |
10/334465 |
|
US |