Claims
- 1-48. (Cancelled).
- 49. A method for constructing a molecular nanoblock using chemically assembled electronic nanotechnology, comprising:
forming an array of electrical wires on a substrate via a chemical self-assembly process; aligning the array of electrical wires; combining the array of electrical wires and forming a two dimensional grid-like structure; and creating an active electronic device at an intersection point of two wires on the grid-like structure.
- 50. The method of claim 49, further comprising fabricating a molecular latch on the grid-like structure.
- 51. The method of claim 50, wherein fabricating a molecular latch further comprises fabricating the molecular latch via an in-line wire fabrication process.
- 52. The method of claim 51, wherein fabricating the molecular latch further comprises:
laying out a first wire in parallel with an input signal wire and output signal wire; bridging a second wire across the first wire, the input wire, and the output wire; and inserting a diode between the input wire and the bridging wire.
- 53. The method of claim 52, wherein fabricating the molecular latch further comprises:
inserting a resistor between the first wire and the output wire; and connecting the output wire to ground at a point where the output wire crosses the bridging wire.
- 54. The method of claim 49, wherein creating an active electronic device at an intersection point of two wires on the grid further comprises creating a reconfigurable molecular diode at an intersection point of the grid-like structure.
- 55. The method of claim 49, further comprising generating a defect map of the grid-like structure.
- 56. The method of claim 55, further comprising reconfiguring a functionality of the grid-like structure according to the defect map.
- 57. A method of fabricating a chemically assembled electronic nanotechnology molecular latch, comprising:
forming a first resonant tunneling diode having a first end and a second end on a chemically assembled electronic nanotechnology grid-like structure forming a nanoblock; connecting a second resonant tunneling diode having a first end and a second end to the first resonant tunneling diode and forming a data node therebetween, wherein the second end of the first resonant tunneling diode is connected to the first end of the second resonant tunneling diode; and connecting an isolation circuit to the data node.
- 58. The method of claim 57, further comprising connecting the first end of the first resonant tunneling diode to a clock signal.
- 59. The method of claim 58, wherein connecting the first end of the first resonant tunneling diode to a clock signal further comprises connecting the first end of the first resonant tunneling diode to a two-phase clock signal.
- 60. The method of claim 57, wherein connecting the isolation circuit further comprises connecting the second end of the second resonant tunneling diode to ground.
- 61. The method of claim 57, wherein connecting the isolation circuit further comprises connecting a molecular diode to the data node of the molecular latch.
- 62. The method of claim 57, wherein connecting the isolation circuit further comprises connecting a resistor between the data node and the output of the molecular latch.
- 63. The method of claim 57, wherein connecting the isolation circuit further comprises connecting a resistor between the output of the molecular latch and ground.
- 64. A method of fabricating a chemically assembled electronic nanotechnology circuit, comprising:
forming a chemically assembled electronic nanotechnology molecular nano-fabric; forming a plurality of clusters on the nano-fabric; forming a plurality of long lines and adjacently disposing the long lines to each of the clusters for communicating signals between the clusters; and forming a nanoblock in at least one of the clusters and connecting an in-line latch to the nanoblock.
- 65. The method of claim 64, wherein forming the nanoblock further comprises forming an input and an output on the nanoblock for implementing a logic function.
- 66. The method of claim 64, wherein forming the input and the output on the nanoblock further comprises forming a set of three Input/Output lines on the nanoblock.
- 67. The method of claim 64, wherein forming the nanoblock further comprises forming a matrix of reconfigurable diodes therein.
- 68. The method of claim 64, wherein forming the nanoblock further comprises forming a molecular logic array therein.
- 69. The method of claim 68, wherein forming the molecular logic array further comprises forming at least two orthogonal sets of wires forming a configurable molecular switch at each intersection of the two orthogonal sets of wires.
- 70. The method of claim 64, further comprising configuring the molecular switch as a diode.
- 71. The method of claim 64, further comprising connecting the nanoblock to neighboring nanoblocks.
- 72. The method of claim 71, further comprising interconnecting four surrounding nanoblocks via the Input/Output portions of each of the four nanoblocks, wherein first and second nanoblocks are arranged in a South and East configuration and third and fourth nanoblocks are arranged in a North and West configuration.
- 73. The method of claim 64, further comprising configuring the nanoblock to implement any of a AND, OR, XOR, and ADDER logic circuit element.
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Application No. 60/281,168, filed Apr. 3, 2001.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH AND DEVELOPMENT
[0002] This work was supported in part under DARPA #: Nz4000140110659. The United States government may have certain rights to this invention.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60281168 |
Apr 2001 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
10116501 |
Apr 2002 |
US |
Child |
10889294 |
Jul 2004 |
US |